core/stdarch/crates/core_arch/src/hexagon/
scalar.rs

1// This code is automatically generated. DO NOT MODIFY.
2//! Hexagon scalar intrinsics
3//!
4//! This module provides intrinsics for scalar (non-HVX) Hexagon DSP operations,
5//! including arithmetic, multiply, shift, saturate, compare, and floating-point
6//! operations.
7//!
8//! [Hexagon V68 Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-45)
9//!
10//! ## Naming Convention
11//!
12//! Function names preserve the original Q6 naming case because the convention
13//! uses case to distinguish register types:
14//! - `P` (uppercase) = 64-bit register pair (`Word64`)
15//! - `p` (lowercase) = predicate register (`Byte`)
16//!
17//! For example, `Q6_P_and_PP` operates on 64-bit pairs while `Q6_p_and_pp`
18//! operates on predicate registers.
19//!
20//! ## Architecture Versions
21//!
22//! Most scalar intrinsics are available on all Hexagon architectures.
23//! Some intrinsics require specific architecture versions (v60, v62, v65,
24//! v66, v67, v68, or v67+audio) and carry
25//! `#[target_feature(enable = "v68")]` (or the appropriate version).
26//! Enable these with `-C target-feature=+v68` or by setting the target CPU
27//! via `-C target-cpu=hexagonv68`.
28//!
29//! Each version includes all features from previous versions.
30
31#![allow(non_snake_case)]
32
33#[cfg(test)]
34use stdarch_test::assert_instr;
35
36// LLVM intrinsic declarations for Hexagon scalar operations
37#[allow(improper_ctypes)]
38unsafe extern "unadjusted" {
39    #[link_name = "llvm.hexagon.A2.abs"]
40    fn hexagon_A2_abs(_: i32) -> i32;
41    #[link_name = "llvm.hexagon.A2.absp"]
42    fn hexagon_A2_absp(_: i64) -> i64;
43    #[link_name = "llvm.hexagon.A2.abssat"]
44    fn hexagon_A2_abssat(_: i32) -> i32;
45    #[link_name = "llvm.hexagon.A2.add"]
46    fn hexagon_A2_add(_: i32, _: i32) -> i32;
47    #[link_name = "llvm.hexagon.A2.addh.h16.hh"]
48    fn hexagon_A2_addh_h16_hh(_: i32, _: i32) -> i32;
49    #[link_name = "llvm.hexagon.A2.addh.h16.hl"]
50    fn hexagon_A2_addh_h16_hl(_: i32, _: i32) -> i32;
51    #[link_name = "llvm.hexagon.A2.addh.h16.lh"]
52    fn hexagon_A2_addh_h16_lh(_: i32, _: i32) -> i32;
53    #[link_name = "llvm.hexagon.A2.addh.h16.ll"]
54    fn hexagon_A2_addh_h16_ll(_: i32, _: i32) -> i32;
55    #[link_name = "llvm.hexagon.A2.addh.h16.sat.hh"]
56    fn hexagon_A2_addh_h16_sat_hh(_: i32, _: i32) -> i32;
57    #[link_name = "llvm.hexagon.A2.addh.h16.sat.hl"]
58    fn hexagon_A2_addh_h16_sat_hl(_: i32, _: i32) -> i32;
59    #[link_name = "llvm.hexagon.A2.addh.h16.sat.lh"]
60    fn hexagon_A2_addh_h16_sat_lh(_: i32, _: i32) -> i32;
61    #[link_name = "llvm.hexagon.A2.addh.h16.sat.ll"]
62    fn hexagon_A2_addh_h16_sat_ll(_: i32, _: i32) -> i32;
63    #[link_name = "llvm.hexagon.A2.addh.l16.hl"]
64    fn hexagon_A2_addh_l16_hl(_: i32, _: i32) -> i32;
65    #[link_name = "llvm.hexagon.A2.addh.l16.ll"]
66    fn hexagon_A2_addh_l16_ll(_: i32, _: i32) -> i32;
67    #[link_name = "llvm.hexagon.A2.addh.l16.sat.hl"]
68    fn hexagon_A2_addh_l16_sat_hl(_: i32, _: i32) -> i32;
69    #[link_name = "llvm.hexagon.A2.addh.l16.sat.ll"]
70    fn hexagon_A2_addh_l16_sat_ll(_: i32, _: i32) -> i32;
71    #[link_name = "llvm.hexagon.A2.addi"]
72    fn hexagon_A2_addi(_: i32, _: i32) -> i32;
73    #[link_name = "llvm.hexagon.A2.addp"]
74    fn hexagon_A2_addp(_: i64, _: i64) -> i64;
75    #[link_name = "llvm.hexagon.A2.addpsat"]
76    fn hexagon_A2_addpsat(_: i64, _: i64) -> i64;
77    #[link_name = "llvm.hexagon.A2.addsat"]
78    fn hexagon_A2_addsat(_: i32, _: i32) -> i32;
79    #[link_name = "llvm.hexagon.A2.addsp"]
80    fn hexagon_A2_addsp(_: i32, _: i64) -> i64;
81    #[link_name = "llvm.hexagon.A2.and"]
82    fn hexagon_A2_and(_: i32, _: i32) -> i32;
83    #[link_name = "llvm.hexagon.A2.andir"]
84    fn hexagon_A2_andir(_: i32, _: i32) -> i32;
85    #[link_name = "llvm.hexagon.A2.andp"]
86    fn hexagon_A2_andp(_: i64, _: i64) -> i64;
87    #[link_name = "llvm.hexagon.A2.aslh"]
88    fn hexagon_A2_aslh(_: i32) -> i32;
89    #[link_name = "llvm.hexagon.A2.asrh"]
90    fn hexagon_A2_asrh(_: i32) -> i32;
91    #[link_name = "llvm.hexagon.A2.combine.hh"]
92    fn hexagon_A2_combine_hh(_: i32, _: i32) -> i32;
93    #[link_name = "llvm.hexagon.A2.combine.hl"]
94    fn hexagon_A2_combine_hl(_: i32, _: i32) -> i32;
95    #[link_name = "llvm.hexagon.A2.combine.lh"]
96    fn hexagon_A2_combine_lh(_: i32, _: i32) -> i32;
97    #[link_name = "llvm.hexagon.A2.combine.ll"]
98    fn hexagon_A2_combine_ll(_: i32, _: i32) -> i32;
99    #[link_name = "llvm.hexagon.A2.combineii"]
100    fn hexagon_A2_combineii(_: i32, _: i32) -> i64;
101    #[link_name = "llvm.hexagon.A2.combinew"]
102    fn hexagon_A2_combinew(_: i32, _: i32) -> i64;
103    #[link_name = "llvm.hexagon.A2.max"]
104    fn hexagon_A2_max(_: i32, _: i32) -> i32;
105    #[link_name = "llvm.hexagon.A2.maxp"]
106    fn hexagon_A2_maxp(_: i64, _: i64) -> i64;
107    #[link_name = "llvm.hexagon.A2.maxu"]
108    fn hexagon_A2_maxu(_: i32, _: i32) -> i32;
109    #[link_name = "llvm.hexagon.A2.maxup"]
110    fn hexagon_A2_maxup(_: i64, _: i64) -> i64;
111    #[link_name = "llvm.hexagon.A2.min"]
112    fn hexagon_A2_min(_: i32, _: i32) -> i32;
113    #[link_name = "llvm.hexagon.A2.minp"]
114    fn hexagon_A2_minp(_: i64, _: i64) -> i64;
115    #[link_name = "llvm.hexagon.A2.minu"]
116    fn hexagon_A2_minu(_: i32, _: i32) -> i32;
117    #[link_name = "llvm.hexagon.A2.minup"]
118    fn hexagon_A2_minup(_: i64, _: i64) -> i64;
119    #[link_name = "llvm.hexagon.A2.neg"]
120    fn hexagon_A2_neg(_: i32) -> i32;
121    #[link_name = "llvm.hexagon.A2.negp"]
122    fn hexagon_A2_negp(_: i64) -> i64;
123    #[link_name = "llvm.hexagon.A2.negsat"]
124    fn hexagon_A2_negsat(_: i32) -> i32;
125    #[link_name = "llvm.hexagon.A2.not"]
126    fn hexagon_A2_not(_: i32) -> i32;
127    #[link_name = "llvm.hexagon.A2.notp"]
128    fn hexagon_A2_notp(_: i64) -> i64;
129    #[link_name = "llvm.hexagon.A2.or"]
130    fn hexagon_A2_or(_: i32, _: i32) -> i32;
131    #[link_name = "llvm.hexagon.A2.orir"]
132    fn hexagon_A2_orir(_: i32, _: i32) -> i32;
133    #[link_name = "llvm.hexagon.A2.orp"]
134    fn hexagon_A2_orp(_: i64, _: i64) -> i64;
135    #[link_name = "llvm.hexagon.A2.roundsat"]
136    fn hexagon_A2_roundsat(_: i64) -> i32;
137    #[link_name = "llvm.hexagon.A2.sat"]
138    fn hexagon_A2_sat(_: i64) -> i32;
139    #[link_name = "llvm.hexagon.A2.satb"]
140    fn hexagon_A2_satb(_: i32) -> i32;
141    #[link_name = "llvm.hexagon.A2.sath"]
142    fn hexagon_A2_sath(_: i32) -> i32;
143    #[link_name = "llvm.hexagon.A2.satub"]
144    fn hexagon_A2_satub(_: i32) -> i32;
145    #[link_name = "llvm.hexagon.A2.satuh"]
146    fn hexagon_A2_satuh(_: i32) -> i32;
147    #[link_name = "llvm.hexagon.A2.sub"]
148    fn hexagon_A2_sub(_: i32, _: i32) -> i32;
149    #[link_name = "llvm.hexagon.A2.subh.h16.hh"]
150    fn hexagon_A2_subh_h16_hh(_: i32, _: i32) -> i32;
151    #[link_name = "llvm.hexagon.A2.subh.h16.hl"]
152    fn hexagon_A2_subh_h16_hl(_: i32, _: i32) -> i32;
153    #[link_name = "llvm.hexagon.A2.subh.h16.lh"]
154    fn hexagon_A2_subh_h16_lh(_: i32, _: i32) -> i32;
155    #[link_name = "llvm.hexagon.A2.subh.h16.ll"]
156    fn hexagon_A2_subh_h16_ll(_: i32, _: i32) -> i32;
157    #[link_name = "llvm.hexagon.A2.subh.h16.sat.hh"]
158    fn hexagon_A2_subh_h16_sat_hh(_: i32, _: i32) -> i32;
159    #[link_name = "llvm.hexagon.A2.subh.h16.sat.hl"]
160    fn hexagon_A2_subh_h16_sat_hl(_: i32, _: i32) -> i32;
161    #[link_name = "llvm.hexagon.A2.subh.h16.sat.lh"]
162    fn hexagon_A2_subh_h16_sat_lh(_: i32, _: i32) -> i32;
163    #[link_name = "llvm.hexagon.A2.subh.h16.sat.ll"]
164    fn hexagon_A2_subh_h16_sat_ll(_: i32, _: i32) -> i32;
165    #[link_name = "llvm.hexagon.A2.subh.l16.hl"]
166    fn hexagon_A2_subh_l16_hl(_: i32, _: i32) -> i32;
167    #[link_name = "llvm.hexagon.A2.subh.l16.ll"]
168    fn hexagon_A2_subh_l16_ll(_: i32, _: i32) -> i32;
169    #[link_name = "llvm.hexagon.A2.subh.l16.sat.hl"]
170    fn hexagon_A2_subh_l16_sat_hl(_: i32, _: i32) -> i32;
171    #[link_name = "llvm.hexagon.A2.subh.l16.sat.ll"]
172    fn hexagon_A2_subh_l16_sat_ll(_: i32, _: i32) -> i32;
173    #[link_name = "llvm.hexagon.A2.subp"]
174    fn hexagon_A2_subp(_: i64, _: i64) -> i64;
175    #[link_name = "llvm.hexagon.A2.subri"]
176    fn hexagon_A2_subri(_: i32, _: i32) -> i32;
177    #[link_name = "llvm.hexagon.A2.subsat"]
178    fn hexagon_A2_subsat(_: i32, _: i32) -> i32;
179    #[link_name = "llvm.hexagon.A2.svaddh"]
180    fn hexagon_A2_svaddh(_: i32, _: i32) -> i32;
181    #[link_name = "llvm.hexagon.A2.svaddhs"]
182    fn hexagon_A2_svaddhs(_: i32, _: i32) -> i32;
183    #[link_name = "llvm.hexagon.A2.svadduhs"]
184    fn hexagon_A2_svadduhs(_: i32, _: i32) -> i32;
185    #[link_name = "llvm.hexagon.A2.svavgh"]
186    fn hexagon_A2_svavgh(_: i32, _: i32) -> i32;
187    #[link_name = "llvm.hexagon.A2.svavghs"]
188    fn hexagon_A2_svavghs(_: i32, _: i32) -> i32;
189    #[link_name = "llvm.hexagon.A2.svnavgh"]
190    fn hexagon_A2_svnavgh(_: i32, _: i32) -> i32;
191    #[link_name = "llvm.hexagon.A2.svsubh"]
192    fn hexagon_A2_svsubh(_: i32, _: i32) -> i32;
193    #[link_name = "llvm.hexagon.A2.svsubhs"]
194    fn hexagon_A2_svsubhs(_: i32, _: i32) -> i32;
195    #[link_name = "llvm.hexagon.A2.svsubuhs"]
196    fn hexagon_A2_svsubuhs(_: i32, _: i32) -> i32;
197    #[link_name = "llvm.hexagon.A2.swiz"]
198    fn hexagon_A2_swiz(_: i32) -> i32;
199    #[link_name = "llvm.hexagon.A2.sxtb"]
200    fn hexagon_A2_sxtb(_: i32) -> i32;
201    #[link_name = "llvm.hexagon.A2.sxth"]
202    fn hexagon_A2_sxth(_: i32) -> i32;
203    #[link_name = "llvm.hexagon.A2.sxtw"]
204    fn hexagon_A2_sxtw(_: i32) -> i64;
205    #[link_name = "llvm.hexagon.A2.tfr"]
206    fn hexagon_A2_tfr(_: i32) -> i32;
207    #[link_name = "llvm.hexagon.A2.tfrih"]
208    fn hexagon_A2_tfrih(_: i32, _: i32) -> i32;
209    #[link_name = "llvm.hexagon.A2.tfril"]
210    fn hexagon_A2_tfril(_: i32, _: i32) -> i32;
211    #[link_name = "llvm.hexagon.A2.tfrp"]
212    fn hexagon_A2_tfrp(_: i64) -> i64;
213    #[link_name = "llvm.hexagon.A2.tfrpi"]
214    fn hexagon_A2_tfrpi(_: i32) -> i64;
215    #[link_name = "llvm.hexagon.A2.tfrsi"]
216    fn hexagon_A2_tfrsi(_: i32) -> i32;
217    #[link_name = "llvm.hexagon.A2.vabsh"]
218    fn hexagon_A2_vabsh(_: i64) -> i64;
219    #[link_name = "llvm.hexagon.A2.vabshsat"]
220    fn hexagon_A2_vabshsat(_: i64) -> i64;
221    #[link_name = "llvm.hexagon.A2.vabsw"]
222    fn hexagon_A2_vabsw(_: i64) -> i64;
223    #[link_name = "llvm.hexagon.A2.vabswsat"]
224    fn hexagon_A2_vabswsat(_: i64) -> i64;
225    #[link_name = "llvm.hexagon.A2.vaddb.map"]
226    fn hexagon_A2_vaddb_map(_: i64, _: i64) -> i64;
227    #[link_name = "llvm.hexagon.A2.vaddh"]
228    fn hexagon_A2_vaddh(_: i64, _: i64) -> i64;
229    #[link_name = "llvm.hexagon.A2.vaddhs"]
230    fn hexagon_A2_vaddhs(_: i64, _: i64) -> i64;
231    #[link_name = "llvm.hexagon.A2.vaddub"]
232    fn hexagon_A2_vaddub(_: i64, _: i64) -> i64;
233    #[link_name = "llvm.hexagon.A2.vaddubs"]
234    fn hexagon_A2_vaddubs(_: i64, _: i64) -> i64;
235    #[link_name = "llvm.hexagon.A2.vadduhs"]
236    fn hexagon_A2_vadduhs(_: i64, _: i64) -> i64;
237    #[link_name = "llvm.hexagon.A2.vaddw"]
238    fn hexagon_A2_vaddw(_: i64, _: i64) -> i64;
239    #[link_name = "llvm.hexagon.A2.vaddws"]
240    fn hexagon_A2_vaddws(_: i64, _: i64) -> i64;
241    #[link_name = "llvm.hexagon.A2.vavgh"]
242    fn hexagon_A2_vavgh(_: i64, _: i64) -> i64;
243    #[link_name = "llvm.hexagon.A2.vavghcr"]
244    fn hexagon_A2_vavghcr(_: i64, _: i64) -> i64;
245    #[link_name = "llvm.hexagon.A2.vavghr"]
246    fn hexagon_A2_vavghr(_: i64, _: i64) -> i64;
247    #[link_name = "llvm.hexagon.A2.vavgub"]
248    fn hexagon_A2_vavgub(_: i64, _: i64) -> i64;
249    #[link_name = "llvm.hexagon.A2.vavgubr"]
250    fn hexagon_A2_vavgubr(_: i64, _: i64) -> i64;
251    #[link_name = "llvm.hexagon.A2.vavguh"]
252    fn hexagon_A2_vavguh(_: i64, _: i64) -> i64;
253    #[link_name = "llvm.hexagon.A2.vavguhr"]
254    fn hexagon_A2_vavguhr(_: i64, _: i64) -> i64;
255    #[link_name = "llvm.hexagon.A2.vavguw"]
256    fn hexagon_A2_vavguw(_: i64, _: i64) -> i64;
257    #[link_name = "llvm.hexagon.A2.vavguwr"]
258    fn hexagon_A2_vavguwr(_: i64, _: i64) -> i64;
259    #[link_name = "llvm.hexagon.A2.vavgw"]
260    fn hexagon_A2_vavgw(_: i64, _: i64) -> i64;
261    #[link_name = "llvm.hexagon.A2.vavgwcr"]
262    fn hexagon_A2_vavgwcr(_: i64, _: i64) -> i64;
263    #[link_name = "llvm.hexagon.A2.vavgwr"]
264    fn hexagon_A2_vavgwr(_: i64, _: i64) -> i64;
265    #[link_name = "llvm.hexagon.A2.vcmpbeq"]
266    fn hexagon_A2_vcmpbeq(_: i64, _: i64) -> i32;
267    #[link_name = "llvm.hexagon.A2.vcmpbgtu"]
268    fn hexagon_A2_vcmpbgtu(_: i64, _: i64) -> i32;
269    #[link_name = "llvm.hexagon.A2.vcmpheq"]
270    fn hexagon_A2_vcmpheq(_: i64, _: i64) -> i32;
271    #[link_name = "llvm.hexagon.A2.vcmphgt"]
272    fn hexagon_A2_vcmphgt(_: i64, _: i64) -> i32;
273    #[link_name = "llvm.hexagon.A2.vcmphgtu"]
274    fn hexagon_A2_vcmphgtu(_: i64, _: i64) -> i32;
275    #[link_name = "llvm.hexagon.A2.vcmpweq"]
276    fn hexagon_A2_vcmpweq(_: i64, _: i64) -> i32;
277    #[link_name = "llvm.hexagon.A2.vcmpwgt"]
278    fn hexagon_A2_vcmpwgt(_: i64, _: i64) -> i32;
279    #[link_name = "llvm.hexagon.A2.vcmpwgtu"]
280    fn hexagon_A2_vcmpwgtu(_: i64, _: i64) -> i32;
281    #[link_name = "llvm.hexagon.A2.vconj"]
282    fn hexagon_A2_vconj(_: i64) -> i64;
283    #[link_name = "llvm.hexagon.A2.vmaxb"]
284    fn hexagon_A2_vmaxb(_: i64, _: i64) -> i64;
285    #[link_name = "llvm.hexagon.A2.vmaxh"]
286    fn hexagon_A2_vmaxh(_: i64, _: i64) -> i64;
287    #[link_name = "llvm.hexagon.A2.vmaxub"]
288    fn hexagon_A2_vmaxub(_: i64, _: i64) -> i64;
289    #[link_name = "llvm.hexagon.A2.vmaxuh"]
290    fn hexagon_A2_vmaxuh(_: i64, _: i64) -> i64;
291    #[link_name = "llvm.hexagon.A2.vmaxuw"]
292    fn hexagon_A2_vmaxuw(_: i64, _: i64) -> i64;
293    #[link_name = "llvm.hexagon.A2.vmaxw"]
294    fn hexagon_A2_vmaxw(_: i64, _: i64) -> i64;
295    #[link_name = "llvm.hexagon.A2.vminb"]
296    fn hexagon_A2_vminb(_: i64, _: i64) -> i64;
297    #[link_name = "llvm.hexagon.A2.vminh"]
298    fn hexagon_A2_vminh(_: i64, _: i64) -> i64;
299    #[link_name = "llvm.hexagon.A2.vminub"]
300    fn hexagon_A2_vminub(_: i64, _: i64) -> i64;
301    #[link_name = "llvm.hexagon.A2.vminuh"]
302    fn hexagon_A2_vminuh(_: i64, _: i64) -> i64;
303    #[link_name = "llvm.hexagon.A2.vminuw"]
304    fn hexagon_A2_vminuw(_: i64, _: i64) -> i64;
305    #[link_name = "llvm.hexagon.A2.vminw"]
306    fn hexagon_A2_vminw(_: i64, _: i64) -> i64;
307    #[link_name = "llvm.hexagon.A2.vnavgh"]
308    fn hexagon_A2_vnavgh(_: i64, _: i64) -> i64;
309    #[link_name = "llvm.hexagon.A2.vnavghcr"]
310    fn hexagon_A2_vnavghcr(_: i64, _: i64) -> i64;
311    #[link_name = "llvm.hexagon.A2.vnavghr"]
312    fn hexagon_A2_vnavghr(_: i64, _: i64) -> i64;
313    #[link_name = "llvm.hexagon.A2.vnavgw"]
314    fn hexagon_A2_vnavgw(_: i64, _: i64) -> i64;
315    #[link_name = "llvm.hexagon.A2.vnavgwcr"]
316    fn hexagon_A2_vnavgwcr(_: i64, _: i64) -> i64;
317    #[link_name = "llvm.hexagon.A2.vnavgwr"]
318    fn hexagon_A2_vnavgwr(_: i64, _: i64) -> i64;
319    #[link_name = "llvm.hexagon.A2.vraddub"]
320    fn hexagon_A2_vraddub(_: i64, _: i64) -> i64;
321    #[link_name = "llvm.hexagon.A2.vraddub.acc"]
322    fn hexagon_A2_vraddub_acc(_: i64, _: i64, _: i64) -> i64;
323    #[link_name = "llvm.hexagon.A2.vrsadub"]
324    fn hexagon_A2_vrsadub(_: i64, _: i64) -> i64;
325    #[link_name = "llvm.hexagon.A2.vrsadub.acc"]
326    fn hexagon_A2_vrsadub_acc(_: i64, _: i64, _: i64) -> i64;
327    #[link_name = "llvm.hexagon.A2.vsubb.map"]
328    fn hexagon_A2_vsubb_map(_: i64, _: i64) -> i64;
329    #[link_name = "llvm.hexagon.A2.vsubh"]
330    fn hexagon_A2_vsubh(_: i64, _: i64) -> i64;
331    #[link_name = "llvm.hexagon.A2.vsubhs"]
332    fn hexagon_A2_vsubhs(_: i64, _: i64) -> i64;
333    #[link_name = "llvm.hexagon.A2.vsubub"]
334    fn hexagon_A2_vsubub(_: i64, _: i64) -> i64;
335    #[link_name = "llvm.hexagon.A2.vsububs"]
336    fn hexagon_A2_vsububs(_: i64, _: i64) -> i64;
337    #[link_name = "llvm.hexagon.A2.vsubuhs"]
338    fn hexagon_A2_vsubuhs(_: i64, _: i64) -> i64;
339    #[link_name = "llvm.hexagon.A2.vsubw"]
340    fn hexagon_A2_vsubw(_: i64, _: i64) -> i64;
341    #[link_name = "llvm.hexagon.A2.vsubws"]
342    fn hexagon_A2_vsubws(_: i64, _: i64) -> i64;
343    #[link_name = "llvm.hexagon.A2.xor"]
344    fn hexagon_A2_xor(_: i32, _: i32) -> i32;
345    #[link_name = "llvm.hexagon.A2.xorp"]
346    fn hexagon_A2_xorp(_: i64, _: i64) -> i64;
347    #[link_name = "llvm.hexagon.A2.zxtb"]
348    fn hexagon_A2_zxtb(_: i32) -> i32;
349    #[link_name = "llvm.hexagon.A2.zxth"]
350    fn hexagon_A2_zxth(_: i32) -> i32;
351    #[link_name = "llvm.hexagon.A4.andn"]
352    fn hexagon_A4_andn(_: i32, _: i32) -> i32;
353    #[link_name = "llvm.hexagon.A4.andnp"]
354    fn hexagon_A4_andnp(_: i64, _: i64) -> i64;
355    #[link_name = "llvm.hexagon.A4.bitsplit"]
356    fn hexagon_A4_bitsplit(_: i32, _: i32) -> i64;
357    #[link_name = "llvm.hexagon.A4.bitspliti"]
358    fn hexagon_A4_bitspliti(_: i32, _: i32) -> i64;
359    #[link_name = "llvm.hexagon.A4.boundscheck"]
360    fn hexagon_A4_boundscheck(_: i32, _: i64) -> i32;
361    #[link_name = "llvm.hexagon.A4.cmpbeq"]
362    fn hexagon_A4_cmpbeq(_: i32, _: i32) -> i32;
363    #[link_name = "llvm.hexagon.A4.cmpbeqi"]
364    fn hexagon_A4_cmpbeqi(_: i32, _: i32) -> i32;
365    #[link_name = "llvm.hexagon.A4.cmpbgt"]
366    fn hexagon_A4_cmpbgt(_: i32, _: i32) -> i32;
367    #[link_name = "llvm.hexagon.A4.cmpbgti"]
368    fn hexagon_A4_cmpbgti(_: i32, _: i32) -> i32;
369    #[link_name = "llvm.hexagon.A4.cmpbgtu"]
370    fn hexagon_A4_cmpbgtu(_: i32, _: i32) -> i32;
371    #[link_name = "llvm.hexagon.A4.cmpbgtui"]
372    fn hexagon_A4_cmpbgtui(_: i32, _: i32) -> i32;
373    #[link_name = "llvm.hexagon.A4.cmpheq"]
374    fn hexagon_A4_cmpheq(_: i32, _: i32) -> i32;
375    #[link_name = "llvm.hexagon.A4.cmpheqi"]
376    fn hexagon_A4_cmpheqi(_: i32, _: i32) -> i32;
377    #[link_name = "llvm.hexagon.A4.cmphgt"]
378    fn hexagon_A4_cmphgt(_: i32, _: i32) -> i32;
379    #[link_name = "llvm.hexagon.A4.cmphgti"]
380    fn hexagon_A4_cmphgti(_: i32, _: i32) -> i32;
381    #[link_name = "llvm.hexagon.A4.cmphgtu"]
382    fn hexagon_A4_cmphgtu(_: i32, _: i32) -> i32;
383    #[link_name = "llvm.hexagon.A4.cmphgtui"]
384    fn hexagon_A4_cmphgtui(_: i32, _: i32) -> i32;
385    #[link_name = "llvm.hexagon.A4.combineir"]
386    fn hexagon_A4_combineir(_: i32, _: i32) -> i64;
387    #[link_name = "llvm.hexagon.A4.combineri"]
388    fn hexagon_A4_combineri(_: i32, _: i32) -> i64;
389    #[link_name = "llvm.hexagon.A4.cround.ri"]
390    fn hexagon_A4_cround_ri(_: i32, _: i32) -> i32;
391    #[link_name = "llvm.hexagon.A4.cround.rr"]
392    fn hexagon_A4_cround_rr(_: i32, _: i32) -> i32;
393    #[link_name = "llvm.hexagon.A4.modwrapu"]
394    fn hexagon_A4_modwrapu(_: i32, _: i32) -> i32;
395    #[link_name = "llvm.hexagon.A4.orn"]
396    fn hexagon_A4_orn(_: i32, _: i32) -> i32;
397    #[link_name = "llvm.hexagon.A4.ornp"]
398    fn hexagon_A4_ornp(_: i64, _: i64) -> i64;
399    #[link_name = "llvm.hexagon.A4.rcmpeq"]
400    fn hexagon_A4_rcmpeq(_: i32, _: i32) -> i32;
401    #[link_name = "llvm.hexagon.A4.rcmpeqi"]
402    fn hexagon_A4_rcmpeqi(_: i32, _: i32) -> i32;
403    #[link_name = "llvm.hexagon.A4.rcmpneq"]
404    fn hexagon_A4_rcmpneq(_: i32, _: i32) -> i32;
405    #[link_name = "llvm.hexagon.A4.rcmpneqi"]
406    fn hexagon_A4_rcmpneqi(_: i32, _: i32) -> i32;
407    #[link_name = "llvm.hexagon.A4.round.ri"]
408    fn hexagon_A4_round_ri(_: i32, _: i32) -> i32;
409    #[link_name = "llvm.hexagon.A4.round.ri.sat"]
410    fn hexagon_A4_round_ri_sat(_: i32, _: i32) -> i32;
411    #[link_name = "llvm.hexagon.A4.round.rr"]
412    fn hexagon_A4_round_rr(_: i32, _: i32) -> i32;
413    #[link_name = "llvm.hexagon.A4.round.rr.sat"]
414    fn hexagon_A4_round_rr_sat(_: i32, _: i32) -> i32;
415    #[link_name = "llvm.hexagon.A4.tlbmatch"]
416    fn hexagon_A4_tlbmatch(_: i64, _: i32) -> i32;
417    #[link_name = "llvm.hexagon.A4.vcmpbeq.any"]
418    fn hexagon_A4_vcmpbeq_any(_: i64, _: i64) -> i32;
419    #[link_name = "llvm.hexagon.A4.vcmpbeqi"]
420    fn hexagon_A4_vcmpbeqi(_: i64, _: i32) -> i32;
421    #[link_name = "llvm.hexagon.A4.vcmpbgt"]
422    fn hexagon_A4_vcmpbgt(_: i64, _: i64) -> i32;
423    #[link_name = "llvm.hexagon.A4.vcmpbgti"]
424    fn hexagon_A4_vcmpbgti(_: i64, _: i32) -> i32;
425    #[link_name = "llvm.hexagon.A4.vcmpbgtui"]
426    fn hexagon_A4_vcmpbgtui(_: i64, _: i32) -> i32;
427    #[link_name = "llvm.hexagon.A4.vcmpheqi"]
428    fn hexagon_A4_vcmpheqi(_: i64, _: i32) -> i32;
429    #[link_name = "llvm.hexagon.A4.vcmphgti"]
430    fn hexagon_A4_vcmphgti(_: i64, _: i32) -> i32;
431    #[link_name = "llvm.hexagon.A4.vcmphgtui"]
432    fn hexagon_A4_vcmphgtui(_: i64, _: i32) -> i32;
433    #[link_name = "llvm.hexagon.A4.vcmpweqi"]
434    fn hexagon_A4_vcmpweqi(_: i64, _: i32) -> i32;
435    #[link_name = "llvm.hexagon.A4.vcmpwgti"]
436    fn hexagon_A4_vcmpwgti(_: i64, _: i32) -> i32;
437    #[link_name = "llvm.hexagon.A4.vcmpwgtui"]
438    fn hexagon_A4_vcmpwgtui(_: i64, _: i32) -> i32;
439    #[link_name = "llvm.hexagon.A4.vrmaxh"]
440    fn hexagon_A4_vrmaxh(_: i64, _: i64, _: i32) -> i64;
441    #[link_name = "llvm.hexagon.A4.vrmaxuh"]
442    fn hexagon_A4_vrmaxuh(_: i64, _: i64, _: i32) -> i64;
443    #[link_name = "llvm.hexagon.A4.vrmaxuw"]
444    fn hexagon_A4_vrmaxuw(_: i64, _: i64, _: i32) -> i64;
445    #[link_name = "llvm.hexagon.A4.vrmaxw"]
446    fn hexagon_A4_vrmaxw(_: i64, _: i64, _: i32) -> i64;
447    #[link_name = "llvm.hexagon.A4.vrminh"]
448    fn hexagon_A4_vrminh(_: i64, _: i64, _: i32) -> i64;
449    #[link_name = "llvm.hexagon.A4.vrminuh"]
450    fn hexagon_A4_vrminuh(_: i64, _: i64, _: i32) -> i64;
451    #[link_name = "llvm.hexagon.A4.vrminuw"]
452    fn hexagon_A4_vrminuw(_: i64, _: i64, _: i32) -> i64;
453    #[link_name = "llvm.hexagon.A4.vrminw"]
454    fn hexagon_A4_vrminw(_: i64, _: i64, _: i32) -> i64;
455    #[link_name = "llvm.hexagon.A5.vaddhubs"]
456    fn hexagon_A5_vaddhubs(_: i64, _: i64) -> i32;
457    #[link_name = "llvm.hexagon.C2.all8"]
458    fn hexagon_C2_all8(_: i32) -> i32;
459    #[link_name = "llvm.hexagon.C2.and"]
460    fn hexagon_C2_and(_: i32, _: i32) -> i32;
461    #[link_name = "llvm.hexagon.C2.andn"]
462    fn hexagon_C2_andn(_: i32, _: i32) -> i32;
463    #[link_name = "llvm.hexagon.C2.any8"]
464    fn hexagon_C2_any8(_: i32) -> i32;
465    #[link_name = "llvm.hexagon.C2.bitsclr"]
466    fn hexagon_C2_bitsclr(_: i32, _: i32) -> i32;
467    #[link_name = "llvm.hexagon.C2.bitsclri"]
468    fn hexagon_C2_bitsclri(_: i32, _: i32) -> i32;
469    #[link_name = "llvm.hexagon.C2.bitsset"]
470    fn hexagon_C2_bitsset(_: i32, _: i32) -> i32;
471    #[link_name = "llvm.hexagon.C2.cmpeq"]
472    fn hexagon_C2_cmpeq(_: i32, _: i32) -> i32;
473    #[link_name = "llvm.hexagon.C2.cmpeqi"]
474    fn hexagon_C2_cmpeqi(_: i32, _: i32) -> i32;
475    #[link_name = "llvm.hexagon.C2.cmpeqp"]
476    fn hexagon_C2_cmpeqp(_: i64, _: i64) -> i32;
477    #[link_name = "llvm.hexagon.C2.cmpgei"]
478    fn hexagon_C2_cmpgei(_: i32, _: i32) -> i32;
479    #[link_name = "llvm.hexagon.C2.cmpgeui"]
480    fn hexagon_C2_cmpgeui(_: i32, _: i32) -> i32;
481    #[link_name = "llvm.hexagon.C2.cmpgt"]
482    fn hexagon_C2_cmpgt(_: i32, _: i32) -> i32;
483    #[link_name = "llvm.hexagon.C2.cmpgti"]
484    fn hexagon_C2_cmpgti(_: i32, _: i32) -> i32;
485    #[link_name = "llvm.hexagon.C2.cmpgtp"]
486    fn hexagon_C2_cmpgtp(_: i64, _: i64) -> i32;
487    #[link_name = "llvm.hexagon.C2.cmpgtu"]
488    fn hexagon_C2_cmpgtu(_: i32, _: i32) -> i32;
489    #[link_name = "llvm.hexagon.C2.cmpgtui"]
490    fn hexagon_C2_cmpgtui(_: i32, _: i32) -> i32;
491    #[link_name = "llvm.hexagon.C2.cmpgtup"]
492    fn hexagon_C2_cmpgtup(_: i64, _: i64) -> i32;
493    #[link_name = "llvm.hexagon.C2.cmplt"]
494    fn hexagon_C2_cmplt(_: i32, _: i32) -> i32;
495    #[link_name = "llvm.hexagon.C2.cmpltu"]
496    fn hexagon_C2_cmpltu(_: i32, _: i32) -> i32;
497    #[link_name = "llvm.hexagon.C2.mask"]
498    fn hexagon_C2_mask(_: i32) -> i64;
499    #[link_name = "llvm.hexagon.C2.mux"]
500    fn hexagon_C2_mux(_: i32, _: i32, _: i32) -> i32;
501    #[link_name = "llvm.hexagon.C2.muxii"]
502    fn hexagon_C2_muxii(_: i32, _: i32, _: i32) -> i32;
503    #[link_name = "llvm.hexagon.C2.muxir"]
504    fn hexagon_C2_muxir(_: i32, _: i32, _: i32) -> i32;
505    #[link_name = "llvm.hexagon.C2.muxri"]
506    fn hexagon_C2_muxri(_: i32, _: i32, _: i32) -> i32;
507    #[link_name = "llvm.hexagon.C2.not"]
508    fn hexagon_C2_not(_: i32) -> i32;
509    #[link_name = "llvm.hexagon.C2.or"]
510    fn hexagon_C2_or(_: i32, _: i32) -> i32;
511    #[link_name = "llvm.hexagon.C2.orn"]
512    fn hexagon_C2_orn(_: i32, _: i32) -> i32;
513    #[link_name = "llvm.hexagon.C2.pxfer.map"]
514    fn hexagon_C2_pxfer_map(_: i32) -> i32;
515    #[link_name = "llvm.hexagon.C2.tfrpr"]
516    fn hexagon_C2_tfrpr(_: i32) -> i32;
517    #[link_name = "llvm.hexagon.C2.tfrrp"]
518    fn hexagon_C2_tfrrp(_: i32) -> i32;
519    #[link_name = "llvm.hexagon.C2.vitpack"]
520    fn hexagon_C2_vitpack(_: i32, _: i32) -> i32;
521    #[link_name = "llvm.hexagon.C2.vmux"]
522    fn hexagon_C2_vmux(_: i32, _: i64, _: i64) -> i64;
523    #[link_name = "llvm.hexagon.C2.xor"]
524    fn hexagon_C2_xor(_: i32, _: i32) -> i32;
525    #[link_name = "llvm.hexagon.C4.and.and"]
526    fn hexagon_C4_and_and(_: i32, _: i32, _: i32) -> i32;
527    #[link_name = "llvm.hexagon.C4.and.andn"]
528    fn hexagon_C4_and_andn(_: i32, _: i32, _: i32) -> i32;
529    #[link_name = "llvm.hexagon.C4.and.or"]
530    fn hexagon_C4_and_or(_: i32, _: i32, _: i32) -> i32;
531    #[link_name = "llvm.hexagon.C4.and.orn"]
532    fn hexagon_C4_and_orn(_: i32, _: i32, _: i32) -> i32;
533    #[link_name = "llvm.hexagon.C4.cmplte"]
534    fn hexagon_C4_cmplte(_: i32, _: i32) -> i32;
535    #[link_name = "llvm.hexagon.C4.cmpltei"]
536    fn hexagon_C4_cmpltei(_: i32, _: i32) -> i32;
537    #[link_name = "llvm.hexagon.C4.cmplteu"]
538    fn hexagon_C4_cmplteu(_: i32, _: i32) -> i32;
539    #[link_name = "llvm.hexagon.C4.cmplteui"]
540    fn hexagon_C4_cmplteui(_: i32, _: i32) -> i32;
541    #[link_name = "llvm.hexagon.C4.cmpneq"]
542    fn hexagon_C4_cmpneq(_: i32, _: i32) -> i32;
543    #[link_name = "llvm.hexagon.C4.cmpneqi"]
544    fn hexagon_C4_cmpneqi(_: i32, _: i32) -> i32;
545    #[link_name = "llvm.hexagon.C4.fastcorner9"]
546    fn hexagon_C4_fastcorner9(_: i32, _: i32) -> i32;
547    #[link_name = "llvm.hexagon.C4.fastcorner9.not"]
548    fn hexagon_C4_fastcorner9_not(_: i32, _: i32) -> i32;
549    #[link_name = "llvm.hexagon.C4.nbitsclr"]
550    fn hexagon_C4_nbitsclr(_: i32, _: i32) -> i32;
551    #[link_name = "llvm.hexagon.C4.nbitsclri"]
552    fn hexagon_C4_nbitsclri(_: i32, _: i32) -> i32;
553    #[link_name = "llvm.hexagon.C4.nbitsset"]
554    fn hexagon_C4_nbitsset(_: i32, _: i32) -> i32;
555    #[link_name = "llvm.hexagon.C4.or.and"]
556    fn hexagon_C4_or_and(_: i32, _: i32, _: i32) -> i32;
557    #[link_name = "llvm.hexagon.C4.or.andn"]
558    fn hexagon_C4_or_andn(_: i32, _: i32, _: i32) -> i32;
559    #[link_name = "llvm.hexagon.C4.or.or"]
560    fn hexagon_C4_or_or(_: i32, _: i32, _: i32) -> i32;
561    #[link_name = "llvm.hexagon.C4.or.orn"]
562    fn hexagon_C4_or_orn(_: i32, _: i32, _: i32) -> i32;
563    #[link_name = "llvm.hexagon.F2.conv.d2df"]
564    fn hexagon_F2_conv_d2df(_: i64) -> f64;
565    #[link_name = "llvm.hexagon.F2.conv.d2sf"]
566    fn hexagon_F2_conv_d2sf(_: i64) -> f32;
567    #[link_name = "llvm.hexagon.F2.conv.df2d"]
568    fn hexagon_F2_conv_df2d(_: f64) -> i64;
569    #[link_name = "llvm.hexagon.F2.conv.df2d.chop"]
570    fn hexagon_F2_conv_df2d_chop(_: f64) -> i64;
571    #[link_name = "llvm.hexagon.F2.conv.df2sf"]
572    fn hexagon_F2_conv_df2sf(_: f64) -> f32;
573    #[link_name = "llvm.hexagon.F2.conv.df2ud"]
574    fn hexagon_F2_conv_df2ud(_: f64) -> i64;
575    #[link_name = "llvm.hexagon.F2.conv.df2ud.chop"]
576    fn hexagon_F2_conv_df2ud_chop(_: f64) -> i64;
577    #[link_name = "llvm.hexagon.F2.conv.df2uw"]
578    fn hexagon_F2_conv_df2uw(_: f64) -> i32;
579    #[link_name = "llvm.hexagon.F2.conv.df2uw.chop"]
580    fn hexagon_F2_conv_df2uw_chop(_: f64) -> i32;
581    #[link_name = "llvm.hexagon.F2.conv.df2w"]
582    fn hexagon_F2_conv_df2w(_: f64) -> i32;
583    #[link_name = "llvm.hexagon.F2.conv.df2w.chop"]
584    fn hexagon_F2_conv_df2w_chop(_: f64) -> i32;
585    #[link_name = "llvm.hexagon.F2.conv.sf2d"]
586    fn hexagon_F2_conv_sf2d(_: f32) -> i64;
587    #[link_name = "llvm.hexagon.F2.conv.sf2d.chop"]
588    fn hexagon_F2_conv_sf2d_chop(_: f32) -> i64;
589    #[link_name = "llvm.hexagon.F2.conv.sf2df"]
590    fn hexagon_F2_conv_sf2df(_: f32) -> f64;
591    #[link_name = "llvm.hexagon.F2.conv.sf2ud"]
592    fn hexagon_F2_conv_sf2ud(_: f32) -> i64;
593    #[link_name = "llvm.hexagon.F2.conv.sf2ud.chop"]
594    fn hexagon_F2_conv_sf2ud_chop(_: f32) -> i64;
595    #[link_name = "llvm.hexagon.F2.conv.sf2uw"]
596    fn hexagon_F2_conv_sf2uw(_: f32) -> i32;
597    #[link_name = "llvm.hexagon.F2.conv.sf2uw.chop"]
598    fn hexagon_F2_conv_sf2uw_chop(_: f32) -> i32;
599    #[link_name = "llvm.hexagon.F2.conv.sf2w"]
600    fn hexagon_F2_conv_sf2w(_: f32) -> i32;
601    #[link_name = "llvm.hexagon.F2.conv.sf2w.chop"]
602    fn hexagon_F2_conv_sf2w_chop(_: f32) -> i32;
603    #[link_name = "llvm.hexagon.F2.conv.ud2df"]
604    fn hexagon_F2_conv_ud2df(_: i64) -> f64;
605    #[link_name = "llvm.hexagon.F2.conv.ud2sf"]
606    fn hexagon_F2_conv_ud2sf(_: i64) -> f32;
607    #[link_name = "llvm.hexagon.F2.conv.uw2df"]
608    fn hexagon_F2_conv_uw2df(_: i32) -> f64;
609    #[link_name = "llvm.hexagon.F2.conv.uw2sf"]
610    fn hexagon_F2_conv_uw2sf(_: i32) -> f32;
611    #[link_name = "llvm.hexagon.F2.conv.w2df"]
612    fn hexagon_F2_conv_w2df(_: i32) -> f64;
613    #[link_name = "llvm.hexagon.F2.conv.w2sf"]
614    fn hexagon_F2_conv_w2sf(_: i32) -> f32;
615    #[link_name = "llvm.hexagon.F2.dfclass"]
616    fn hexagon_F2_dfclass(_: f64, _: i32) -> i32;
617    #[link_name = "llvm.hexagon.F2.dfcmpeq"]
618    fn hexagon_F2_dfcmpeq(_: f64, _: f64) -> i32;
619    #[link_name = "llvm.hexagon.F2.dfcmpge"]
620    fn hexagon_F2_dfcmpge(_: f64, _: f64) -> i32;
621    #[link_name = "llvm.hexagon.F2.dfcmpgt"]
622    fn hexagon_F2_dfcmpgt(_: f64, _: f64) -> i32;
623    #[link_name = "llvm.hexagon.F2.dfcmpuo"]
624    fn hexagon_F2_dfcmpuo(_: f64, _: f64) -> i32;
625    #[link_name = "llvm.hexagon.F2.dfimm.n"]
626    fn hexagon_F2_dfimm_n(_: i32) -> f64;
627    #[link_name = "llvm.hexagon.F2.dfimm.p"]
628    fn hexagon_F2_dfimm_p(_: i32) -> f64;
629    #[link_name = "llvm.hexagon.F2.sfadd"]
630    fn hexagon_F2_sfadd(_: f32, _: f32) -> f32;
631    #[link_name = "llvm.hexagon.F2.sfclass"]
632    fn hexagon_F2_sfclass(_: f32, _: i32) -> i32;
633    #[link_name = "llvm.hexagon.F2.sfcmpeq"]
634    fn hexagon_F2_sfcmpeq(_: f32, _: f32) -> i32;
635    #[link_name = "llvm.hexagon.F2.sfcmpge"]
636    fn hexagon_F2_sfcmpge(_: f32, _: f32) -> i32;
637    #[link_name = "llvm.hexagon.F2.sfcmpgt"]
638    fn hexagon_F2_sfcmpgt(_: f32, _: f32) -> i32;
639    #[link_name = "llvm.hexagon.F2.sfcmpuo"]
640    fn hexagon_F2_sfcmpuo(_: f32, _: f32) -> i32;
641    #[link_name = "llvm.hexagon.F2.sffixupd"]
642    fn hexagon_F2_sffixupd(_: f32, _: f32) -> f32;
643    #[link_name = "llvm.hexagon.F2.sffixupn"]
644    fn hexagon_F2_sffixupn(_: f32, _: f32) -> f32;
645    #[link_name = "llvm.hexagon.F2.sffixupr"]
646    fn hexagon_F2_sffixupr(_: f32) -> f32;
647    #[link_name = "llvm.hexagon.F2.sffma"]
648    fn hexagon_F2_sffma(_: f32, _: f32, _: f32) -> f32;
649    #[link_name = "llvm.hexagon.F2.sffma.lib"]
650    fn hexagon_F2_sffma_lib(_: f32, _: f32, _: f32) -> f32;
651    #[link_name = "llvm.hexagon.F2.sffma.sc"]
652    fn hexagon_F2_sffma_sc(_: f32, _: f32, _: f32, _: i32) -> f32;
653    #[link_name = "llvm.hexagon.F2.sffms"]
654    fn hexagon_F2_sffms(_: f32, _: f32, _: f32) -> f32;
655    #[link_name = "llvm.hexagon.F2.sffms.lib"]
656    fn hexagon_F2_sffms_lib(_: f32, _: f32, _: f32) -> f32;
657    #[link_name = "llvm.hexagon.F2.sfimm.n"]
658    fn hexagon_F2_sfimm_n(_: i32) -> f32;
659    #[link_name = "llvm.hexagon.F2.sfimm.p"]
660    fn hexagon_F2_sfimm_p(_: i32) -> f32;
661    #[link_name = "llvm.hexagon.F2.sfmax"]
662    fn hexagon_F2_sfmax(_: f32, _: f32) -> f32;
663    #[link_name = "llvm.hexagon.F2.sfmin"]
664    fn hexagon_F2_sfmin(_: f32, _: f32) -> f32;
665    #[link_name = "llvm.hexagon.F2.sfmpy"]
666    fn hexagon_F2_sfmpy(_: f32, _: f32) -> f32;
667    #[link_name = "llvm.hexagon.F2.sfsub"]
668    fn hexagon_F2_sfsub(_: f32, _: f32) -> f32;
669    #[link_name = "llvm.hexagon.M2.acci"]
670    fn hexagon_M2_acci(_: i32, _: i32, _: i32) -> i32;
671    #[link_name = "llvm.hexagon.M2.accii"]
672    fn hexagon_M2_accii(_: i32, _: i32, _: i32) -> i32;
673    #[link_name = "llvm.hexagon.M2.cmaci.s0"]
674    fn hexagon_M2_cmaci_s0(_: i64, _: i32, _: i32) -> i64;
675    #[link_name = "llvm.hexagon.M2.cmacr.s0"]
676    fn hexagon_M2_cmacr_s0(_: i64, _: i32, _: i32) -> i64;
677    #[link_name = "llvm.hexagon.M2.cmacs.s0"]
678    fn hexagon_M2_cmacs_s0(_: i64, _: i32, _: i32) -> i64;
679    #[link_name = "llvm.hexagon.M2.cmacs.s1"]
680    fn hexagon_M2_cmacs_s1(_: i64, _: i32, _: i32) -> i64;
681    #[link_name = "llvm.hexagon.M2.cmacsc.s0"]
682    fn hexagon_M2_cmacsc_s0(_: i64, _: i32, _: i32) -> i64;
683    #[link_name = "llvm.hexagon.M2.cmacsc.s1"]
684    fn hexagon_M2_cmacsc_s1(_: i64, _: i32, _: i32) -> i64;
685    #[link_name = "llvm.hexagon.M2.cmpyi.s0"]
686    fn hexagon_M2_cmpyi_s0(_: i32, _: i32) -> i64;
687    #[link_name = "llvm.hexagon.M2.cmpyr.s0"]
688    fn hexagon_M2_cmpyr_s0(_: i32, _: i32) -> i64;
689    #[link_name = "llvm.hexagon.M2.cmpyrs.s0"]
690    fn hexagon_M2_cmpyrs_s0(_: i32, _: i32) -> i32;
691    #[link_name = "llvm.hexagon.M2.cmpyrs.s1"]
692    fn hexagon_M2_cmpyrs_s1(_: i32, _: i32) -> i32;
693    #[link_name = "llvm.hexagon.M2.cmpyrsc.s0"]
694    fn hexagon_M2_cmpyrsc_s0(_: i32, _: i32) -> i32;
695    #[link_name = "llvm.hexagon.M2.cmpyrsc.s1"]
696    fn hexagon_M2_cmpyrsc_s1(_: i32, _: i32) -> i32;
697    #[link_name = "llvm.hexagon.M2.cmpys.s0"]
698    fn hexagon_M2_cmpys_s0(_: i32, _: i32) -> i64;
699    #[link_name = "llvm.hexagon.M2.cmpys.s1"]
700    fn hexagon_M2_cmpys_s1(_: i32, _: i32) -> i64;
701    #[link_name = "llvm.hexagon.M2.cmpysc.s0"]
702    fn hexagon_M2_cmpysc_s0(_: i32, _: i32) -> i64;
703    #[link_name = "llvm.hexagon.M2.cmpysc.s1"]
704    fn hexagon_M2_cmpysc_s1(_: i32, _: i32) -> i64;
705    #[link_name = "llvm.hexagon.M2.cnacs.s0"]
706    fn hexagon_M2_cnacs_s0(_: i64, _: i32, _: i32) -> i64;
707    #[link_name = "llvm.hexagon.M2.cnacs.s1"]
708    fn hexagon_M2_cnacs_s1(_: i64, _: i32, _: i32) -> i64;
709    #[link_name = "llvm.hexagon.M2.cnacsc.s0"]
710    fn hexagon_M2_cnacsc_s0(_: i64, _: i32, _: i32) -> i64;
711    #[link_name = "llvm.hexagon.M2.cnacsc.s1"]
712    fn hexagon_M2_cnacsc_s1(_: i64, _: i32, _: i32) -> i64;
713    #[link_name = "llvm.hexagon.M2.dpmpyss.acc.s0"]
714    fn hexagon_M2_dpmpyss_acc_s0(_: i64, _: i32, _: i32) -> i64;
715    #[link_name = "llvm.hexagon.M2.dpmpyss.nac.s0"]
716    fn hexagon_M2_dpmpyss_nac_s0(_: i64, _: i32, _: i32) -> i64;
717    #[link_name = "llvm.hexagon.M2.dpmpyss.rnd.s0"]
718    fn hexagon_M2_dpmpyss_rnd_s0(_: i32, _: i32) -> i32;
719    #[link_name = "llvm.hexagon.M2.dpmpyss.s0"]
720    fn hexagon_M2_dpmpyss_s0(_: i32, _: i32) -> i64;
721    #[link_name = "llvm.hexagon.M2.dpmpyuu.acc.s0"]
722    fn hexagon_M2_dpmpyuu_acc_s0(_: i64, _: i32, _: i32) -> i64;
723    #[link_name = "llvm.hexagon.M2.dpmpyuu.nac.s0"]
724    fn hexagon_M2_dpmpyuu_nac_s0(_: i64, _: i32, _: i32) -> i64;
725    #[link_name = "llvm.hexagon.M2.dpmpyuu.s0"]
726    fn hexagon_M2_dpmpyuu_s0(_: i32, _: i32) -> i64;
727    #[link_name = "llvm.hexagon.M2.hmmpyh.rs1"]
728    fn hexagon_M2_hmmpyh_rs1(_: i32, _: i32) -> i32;
729    #[link_name = "llvm.hexagon.M2.hmmpyh.s1"]
730    fn hexagon_M2_hmmpyh_s1(_: i32, _: i32) -> i32;
731    #[link_name = "llvm.hexagon.M2.hmmpyl.rs1"]
732    fn hexagon_M2_hmmpyl_rs1(_: i32, _: i32) -> i32;
733    #[link_name = "llvm.hexagon.M2.hmmpyl.s1"]
734    fn hexagon_M2_hmmpyl_s1(_: i32, _: i32) -> i32;
735    #[link_name = "llvm.hexagon.M2.maci"]
736    fn hexagon_M2_maci(_: i32, _: i32, _: i32) -> i32;
737    #[link_name = "llvm.hexagon.M2.macsin"]
738    fn hexagon_M2_macsin(_: i32, _: i32, _: i32) -> i32;
739    #[link_name = "llvm.hexagon.M2.macsip"]
740    fn hexagon_M2_macsip(_: i32, _: i32, _: i32) -> i32;
741    #[link_name = "llvm.hexagon.M2.mmachs.rs0"]
742    fn hexagon_M2_mmachs_rs0(_: i64, _: i64, _: i64) -> i64;
743    #[link_name = "llvm.hexagon.M2.mmachs.rs1"]
744    fn hexagon_M2_mmachs_rs1(_: i64, _: i64, _: i64) -> i64;
745    #[link_name = "llvm.hexagon.M2.mmachs.s0"]
746    fn hexagon_M2_mmachs_s0(_: i64, _: i64, _: i64) -> i64;
747    #[link_name = "llvm.hexagon.M2.mmachs.s1"]
748    fn hexagon_M2_mmachs_s1(_: i64, _: i64, _: i64) -> i64;
749    #[link_name = "llvm.hexagon.M2.mmacls.rs0"]
750    fn hexagon_M2_mmacls_rs0(_: i64, _: i64, _: i64) -> i64;
751    #[link_name = "llvm.hexagon.M2.mmacls.rs1"]
752    fn hexagon_M2_mmacls_rs1(_: i64, _: i64, _: i64) -> i64;
753    #[link_name = "llvm.hexagon.M2.mmacls.s0"]
754    fn hexagon_M2_mmacls_s0(_: i64, _: i64, _: i64) -> i64;
755    #[link_name = "llvm.hexagon.M2.mmacls.s1"]
756    fn hexagon_M2_mmacls_s1(_: i64, _: i64, _: i64) -> i64;
757    #[link_name = "llvm.hexagon.M2.mmacuhs.rs0"]
758    fn hexagon_M2_mmacuhs_rs0(_: i64, _: i64, _: i64) -> i64;
759    #[link_name = "llvm.hexagon.M2.mmacuhs.rs1"]
760    fn hexagon_M2_mmacuhs_rs1(_: i64, _: i64, _: i64) -> i64;
761    #[link_name = "llvm.hexagon.M2.mmacuhs.s0"]
762    fn hexagon_M2_mmacuhs_s0(_: i64, _: i64, _: i64) -> i64;
763    #[link_name = "llvm.hexagon.M2.mmacuhs.s1"]
764    fn hexagon_M2_mmacuhs_s1(_: i64, _: i64, _: i64) -> i64;
765    #[link_name = "llvm.hexagon.M2.mmaculs.rs0"]
766    fn hexagon_M2_mmaculs_rs0(_: i64, _: i64, _: i64) -> i64;
767    #[link_name = "llvm.hexagon.M2.mmaculs.rs1"]
768    fn hexagon_M2_mmaculs_rs1(_: i64, _: i64, _: i64) -> i64;
769    #[link_name = "llvm.hexagon.M2.mmaculs.s0"]
770    fn hexagon_M2_mmaculs_s0(_: i64, _: i64, _: i64) -> i64;
771    #[link_name = "llvm.hexagon.M2.mmaculs.s1"]
772    fn hexagon_M2_mmaculs_s1(_: i64, _: i64, _: i64) -> i64;
773    #[link_name = "llvm.hexagon.M2.mmpyh.rs0"]
774    fn hexagon_M2_mmpyh_rs0(_: i64, _: i64) -> i64;
775    #[link_name = "llvm.hexagon.M2.mmpyh.rs1"]
776    fn hexagon_M2_mmpyh_rs1(_: i64, _: i64) -> i64;
777    #[link_name = "llvm.hexagon.M2.mmpyh.s0"]
778    fn hexagon_M2_mmpyh_s0(_: i64, _: i64) -> i64;
779    #[link_name = "llvm.hexagon.M2.mmpyh.s1"]
780    fn hexagon_M2_mmpyh_s1(_: i64, _: i64) -> i64;
781    #[link_name = "llvm.hexagon.M2.mmpyl.rs0"]
782    fn hexagon_M2_mmpyl_rs0(_: i64, _: i64) -> i64;
783    #[link_name = "llvm.hexagon.M2.mmpyl.rs1"]
784    fn hexagon_M2_mmpyl_rs1(_: i64, _: i64) -> i64;
785    #[link_name = "llvm.hexagon.M2.mmpyl.s0"]
786    fn hexagon_M2_mmpyl_s0(_: i64, _: i64) -> i64;
787    #[link_name = "llvm.hexagon.M2.mmpyl.s1"]
788    fn hexagon_M2_mmpyl_s1(_: i64, _: i64) -> i64;
789    #[link_name = "llvm.hexagon.M2.mmpyuh.rs0"]
790    fn hexagon_M2_mmpyuh_rs0(_: i64, _: i64) -> i64;
791    #[link_name = "llvm.hexagon.M2.mmpyuh.rs1"]
792    fn hexagon_M2_mmpyuh_rs1(_: i64, _: i64) -> i64;
793    #[link_name = "llvm.hexagon.M2.mmpyuh.s0"]
794    fn hexagon_M2_mmpyuh_s0(_: i64, _: i64) -> i64;
795    #[link_name = "llvm.hexagon.M2.mmpyuh.s1"]
796    fn hexagon_M2_mmpyuh_s1(_: i64, _: i64) -> i64;
797    #[link_name = "llvm.hexagon.M2.mmpyul.rs0"]
798    fn hexagon_M2_mmpyul_rs0(_: i64, _: i64) -> i64;
799    #[link_name = "llvm.hexagon.M2.mmpyul.rs1"]
800    fn hexagon_M2_mmpyul_rs1(_: i64, _: i64) -> i64;
801    #[link_name = "llvm.hexagon.M2.mmpyul.s0"]
802    fn hexagon_M2_mmpyul_s0(_: i64, _: i64) -> i64;
803    #[link_name = "llvm.hexagon.M2.mmpyul.s1"]
804    fn hexagon_M2_mmpyul_s1(_: i64, _: i64) -> i64;
805    #[link_name = "llvm.hexagon.M2.mpy.acc.hh.s0"]
806    fn hexagon_M2_mpy_acc_hh_s0(_: i32, _: i32, _: i32) -> i32;
807    #[link_name = "llvm.hexagon.M2.mpy.acc.hh.s1"]
808    fn hexagon_M2_mpy_acc_hh_s1(_: i32, _: i32, _: i32) -> i32;
809    #[link_name = "llvm.hexagon.M2.mpy.acc.hl.s0"]
810    fn hexagon_M2_mpy_acc_hl_s0(_: i32, _: i32, _: i32) -> i32;
811    #[link_name = "llvm.hexagon.M2.mpy.acc.hl.s1"]
812    fn hexagon_M2_mpy_acc_hl_s1(_: i32, _: i32, _: i32) -> i32;
813    #[link_name = "llvm.hexagon.M2.mpy.acc.lh.s0"]
814    fn hexagon_M2_mpy_acc_lh_s0(_: i32, _: i32, _: i32) -> i32;
815    #[link_name = "llvm.hexagon.M2.mpy.acc.lh.s1"]
816    fn hexagon_M2_mpy_acc_lh_s1(_: i32, _: i32, _: i32) -> i32;
817    #[link_name = "llvm.hexagon.M2.mpy.acc.ll.s0"]
818    fn hexagon_M2_mpy_acc_ll_s0(_: i32, _: i32, _: i32) -> i32;
819    #[link_name = "llvm.hexagon.M2.mpy.acc.ll.s1"]
820    fn hexagon_M2_mpy_acc_ll_s1(_: i32, _: i32, _: i32) -> i32;
821    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.hh.s0"]
822    fn hexagon_M2_mpy_acc_sat_hh_s0(_: i32, _: i32, _: i32) -> i32;
823    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.hh.s1"]
824    fn hexagon_M2_mpy_acc_sat_hh_s1(_: i32, _: i32, _: i32) -> i32;
825    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.hl.s0"]
826    fn hexagon_M2_mpy_acc_sat_hl_s0(_: i32, _: i32, _: i32) -> i32;
827    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.hl.s1"]
828    fn hexagon_M2_mpy_acc_sat_hl_s1(_: i32, _: i32, _: i32) -> i32;
829    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.lh.s0"]
830    fn hexagon_M2_mpy_acc_sat_lh_s0(_: i32, _: i32, _: i32) -> i32;
831    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.lh.s1"]
832    fn hexagon_M2_mpy_acc_sat_lh_s1(_: i32, _: i32, _: i32) -> i32;
833    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.ll.s0"]
834    fn hexagon_M2_mpy_acc_sat_ll_s0(_: i32, _: i32, _: i32) -> i32;
835    #[link_name = "llvm.hexagon.M2.mpy.acc.sat.ll.s1"]
836    fn hexagon_M2_mpy_acc_sat_ll_s1(_: i32, _: i32, _: i32) -> i32;
837    #[link_name = "llvm.hexagon.M2.mpy.hh.s0"]
838    fn hexagon_M2_mpy_hh_s0(_: i32, _: i32) -> i32;
839    #[link_name = "llvm.hexagon.M2.mpy.hh.s1"]
840    fn hexagon_M2_mpy_hh_s1(_: i32, _: i32) -> i32;
841    #[link_name = "llvm.hexagon.M2.mpy.hl.s0"]
842    fn hexagon_M2_mpy_hl_s0(_: i32, _: i32) -> i32;
843    #[link_name = "llvm.hexagon.M2.mpy.hl.s1"]
844    fn hexagon_M2_mpy_hl_s1(_: i32, _: i32) -> i32;
845    #[link_name = "llvm.hexagon.M2.mpy.lh.s0"]
846    fn hexagon_M2_mpy_lh_s0(_: i32, _: i32) -> i32;
847    #[link_name = "llvm.hexagon.M2.mpy.lh.s1"]
848    fn hexagon_M2_mpy_lh_s1(_: i32, _: i32) -> i32;
849    #[link_name = "llvm.hexagon.M2.mpy.ll.s0"]
850    fn hexagon_M2_mpy_ll_s0(_: i32, _: i32) -> i32;
851    #[link_name = "llvm.hexagon.M2.mpy.ll.s1"]
852    fn hexagon_M2_mpy_ll_s1(_: i32, _: i32) -> i32;
853    #[link_name = "llvm.hexagon.M2.mpy.nac.hh.s0"]
854    fn hexagon_M2_mpy_nac_hh_s0(_: i32, _: i32, _: i32) -> i32;
855    #[link_name = "llvm.hexagon.M2.mpy.nac.hh.s1"]
856    fn hexagon_M2_mpy_nac_hh_s1(_: i32, _: i32, _: i32) -> i32;
857    #[link_name = "llvm.hexagon.M2.mpy.nac.hl.s0"]
858    fn hexagon_M2_mpy_nac_hl_s0(_: i32, _: i32, _: i32) -> i32;
859    #[link_name = "llvm.hexagon.M2.mpy.nac.hl.s1"]
860    fn hexagon_M2_mpy_nac_hl_s1(_: i32, _: i32, _: i32) -> i32;
861    #[link_name = "llvm.hexagon.M2.mpy.nac.lh.s0"]
862    fn hexagon_M2_mpy_nac_lh_s0(_: i32, _: i32, _: i32) -> i32;
863    #[link_name = "llvm.hexagon.M2.mpy.nac.lh.s1"]
864    fn hexagon_M2_mpy_nac_lh_s1(_: i32, _: i32, _: i32) -> i32;
865    #[link_name = "llvm.hexagon.M2.mpy.nac.ll.s0"]
866    fn hexagon_M2_mpy_nac_ll_s0(_: i32, _: i32, _: i32) -> i32;
867    #[link_name = "llvm.hexagon.M2.mpy.nac.ll.s1"]
868    fn hexagon_M2_mpy_nac_ll_s1(_: i32, _: i32, _: i32) -> i32;
869    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.hh.s0"]
870    fn hexagon_M2_mpy_nac_sat_hh_s0(_: i32, _: i32, _: i32) -> i32;
871    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.hh.s1"]
872    fn hexagon_M2_mpy_nac_sat_hh_s1(_: i32, _: i32, _: i32) -> i32;
873    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.hl.s0"]
874    fn hexagon_M2_mpy_nac_sat_hl_s0(_: i32, _: i32, _: i32) -> i32;
875    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.hl.s1"]
876    fn hexagon_M2_mpy_nac_sat_hl_s1(_: i32, _: i32, _: i32) -> i32;
877    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.lh.s0"]
878    fn hexagon_M2_mpy_nac_sat_lh_s0(_: i32, _: i32, _: i32) -> i32;
879    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.lh.s1"]
880    fn hexagon_M2_mpy_nac_sat_lh_s1(_: i32, _: i32, _: i32) -> i32;
881    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.ll.s0"]
882    fn hexagon_M2_mpy_nac_sat_ll_s0(_: i32, _: i32, _: i32) -> i32;
883    #[link_name = "llvm.hexagon.M2.mpy.nac.sat.ll.s1"]
884    fn hexagon_M2_mpy_nac_sat_ll_s1(_: i32, _: i32, _: i32) -> i32;
885    #[link_name = "llvm.hexagon.M2.mpy.rnd.hh.s0"]
886    fn hexagon_M2_mpy_rnd_hh_s0(_: i32, _: i32) -> i32;
887    #[link_name = "llvm.hexagon.M2.mpy.rnd.hh.s1"]
888    fn hexagon_M2_mpy_rnd_hh_s1(_: i32, _: i32) -> i32;
889    #[link_name = "llvm.hexagon.M2.mpy.rnd.hl.s0"]
890    fn hexagon_M2_mpy_rnd_hl_s0(_: i32, _: i32) -> i32;
891    #[link_name = "llvm.hexagon.M2.mpy.rnd.hl.s1"]
892    fn hexagon_M2_mpy_rnd_hl_s1(_: i32, _: i32) -> i32;
893    #[link_name = "llvm.hexagon.M2.mpy.rnd.lh.s0"]
894    fn hexagon_M2_mpy_rnd_lh_s0(_: i32, _: i32) -> i32;
895    #[link_name = "llvm.hexagon.M2.mpy.rnd.lh.s1"]
896    fn hexagon_M2_mpy_rnd_lh_s1(_: i32, _: i32) -> i32;
897    #[link_name = "llvm.hexagon.M2.mpy.rnd.ll.s0"]
898    fn hexagon_M2_mpy_rnd_ll_s0(_: i32, _: i32) -> i32;
899    #[link_name = "llvm.hexagon.M2.mpy.rnd.ll.s1"]
900    fn hexagon_M2_mpy_rnd_ll_s1(_: i32, _: i32) -> i32;
901    #[link_name = "llvm.hexagon.M2.mpy.sat.hh.s0"]
902    fn hexagon_M2_mpy_sat_hh_s0(_: i32, _: i32) -> i32;
903    #[link_name = "llvm.hexagon.M2.mpy.sat.hh.s1"]
904    fn hexagon_M2_mpy_sat_hh_s1(_: i32, _: i32) -> i32;
905    #[link_name = "llvm.hexagon.M2.mpy.sat.hl.s0"]
906    fn hexagon_M2_mpy_sat_hl_s0(_: i32, _: i32) -> i32;
907    #[link_name = "llvm.hexagon.M2.mpy.sat.hl.s1"]
908    fn hexagon_M2_mpy_sat_hl_s1(_: i32, _: i32) -> i32;
909    #[link_name = "llvm.hexagon.M2.mpy.sat.lh.s0"]
910    fn hexagon_M2_mpy_sat_lh_s0(_: i32, _: i32) -> i32;
911    #[link_name = "llvm.hexagon.M2.mpy.sat.lh.s1"]
912    fn hexagon_M2_mpy_sat_lh_s1(_: i32, _: i32) -> i32;
913    #[link_name = "llvm.hexagon.M2.mpy.sat.ll.s0"]
914    fn hexagon_M2_mpy_sat_ll_s0(_: i32, _: i32) -> i32;
915    #[link_name = "llvm.hexagon.M2.mpy.sat.ll.s1"]
916    fn hexagon_M2_mpy_sat_ll_s1(_: i32, _: i32) -> i32;
917    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.hh.s0"]
918    fn hexagon_M2_mpy_sat_rnd_hh_s0(_: i32, _: i32) -> i32;
919    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.hh.s1"]
920    fn hexagon_M2_mpy_sat_rnd_hh_s1(_: i32, _: i32) -> i32;
921    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.hl.s0"]
922    fn hexagon_M2_mpy_sat_rnd_hl_s0(_: i32, _: i32) -> i32;
923    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.hl.s1"]
924    fn hexagon_M2_mpy_sat_rnd_hl_s1(_: i32, _: i32) -> i32;
925    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.lh.s0"]
926    fn hexagon_M2_mpy_sat_rnd_lh_s0(_: i32, _: i32) -> i32;
927    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.lh.s1"]
928    fn hexagon_M2_mpy_sat_rnd_lh_s1(_: i32, _: i32) -> i32;
929    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.ll.s0"]
930    fn hexagon_M2_mpy_sat_rnd_ll_s0(_: i32, _: i32) -> i32;
931    #[link_name = "llvm.hexagon.M2.mpy.sat.rnd.ll.s1"]
932    fn hexagon_M2_mpy_sat_rnd_ll_s1(_: i32, _: i32) -> i32;
933    #[link_name = "llvm.hexagon.M2.mpy.up"]
934    fn hexagon_M2_mpy_up(_: i32, _: i32) -> i32;
935    #[link_name = "llvm.hexagon.M2.mpy.up.s1"]
936    fn hexagon_M2_mpy_up_s1(_: i32, _: i32) -> i32;
937    #[link_name = "llvm.hexagon.M2.mpy.up.s1.sat"]
938    fn hexagon_M2_mpy_up_s1_sat(_: i32, _: i32) -> i32;
939    #[link_name = "llvm.hexagon.M2.mpyd.acc.hh.s0"]
940    fn hexagon_M2_mpyd_acc_hh_s0(_: i64, _: i32, _: i32) -> i64;
941    #[link_name = "llvm.hexagon.M2.mpyd.acc.hh.s1"]
942    fn hexagon_M2_mpyd_acc_hh_s1(_: i64, _: i32, _: i32) -> i64;
943    #[link_name = "llvm.hexagon.M2.mpyd.acc.hl.s0"]
944    fn hexagon_M2_mpyd_acc_hl_s0(_: i64, _: i32, _: i32) -> i64;
945    #[link_name = "llvm.hexagon.M2.mpyd.acc.hl.s1"]
946    fn hexagon_M2_mpyd_acc_hl_s1(_: i64, _: i32, _: i32) -> i64;
947    #[link_name = "llvm.hexagon.M2.mpyd.acc.lh.s0"]
948    fn hexagon_M2_mpyd_acc_lh_s0(_: i64, _: i32, _: i32) -> i64;
949    #[link_name = "llvm.hexagon.M2.mpyd.acc.lh.s1"]
950    fn hexagon_M2_mpyd_acc_lh_s1(_: i64, _: i32, _: i32) -> i64;
951    #[link_name = "llvm.hexagon.M2.mpyd.acc.ll.s0"]
952    fn hexagon_M2_mpyd_acc_ll_s0(_: i64, _: i32, _: i32) -> i64;
953    #[link_name = "llvm.hexagon.M2.mpyd.acc.ll.s1"]
954    fn hexagon_M2_mpyd_acc_ll_s1(_: i64, _: i32, _: i32) -> i64;
955    #[link_name = "llvm.hexagon.M2.mpyd.hh.s0"]
956    fn hexagon_M2_mpyd_hh_s0(_: i32, _: i32) -> i64;
957    #[link_name = "llvm.hexagon.M2.mpyd.hh.s1"]
958    fn hexagon_M2_mpyd_hh_s1(_: i32, _: i32) -> i64;
959    #[link_name = "llvm.hexagon.M2.mpyd.hl.s0"]
960    fn hexagon_M2_mpyd_hl_s0(_: i32, _: i32) -> i64;
961    #[link_name = "llvm.hexagon.M2.mpyd.hl.s1"]
962    fn hexagon_M2_mpyd_hl_s1(_: i32, _: i32) -> i64;
963    #[link_name = "llvm.hexagon.M2.mpyd.lh.s0"]
964    fn hexagon_M2_mpyd_lh_s0(_: i32, _: i32) -> i64;
965    #[link_name = "llvm.hexagon.M2.mpyd.lh.s1"]
966    fn hexagon_M2_mpyd_lh_s1(_: i32, _: i32) -> i64;
967    #[link_name = "llvm.hexagon.M2.mpyd.ll.s0"]
968    fn hexagon_M2_mpyd_ll_s0(_: i32, _: i32) -> i64;
969    #[link_name = "llvm.hexagon.M2.mpyd.ll.s1"]
970    fn hexagon_M2_mpyd_ll_s1(_: i32, _: i32) -> i64;
971    #[link_name = "llvm.hexagon.M2.mpyd.nac.hh.s0"]
972    fn hexagon_M2_mpyd_nac_hh_s0(_: i64, _: i32, _: i32) -> i64;
973    #[link_name = "llvm.hexagon.M2.mpyd.nac.hh.s1"]
974    fn hexagon_M2_mpyd_nac_hh_s1(_: i64, _: i32, _: i32) -> i64;
975    #[link_name = "llvm.hexagon.M2.mpyd.nac.hl.s0"]
976    fn hexagon_M2_mpyd_nac_hl_s0(_: i64, _: i32, _: i32) -> i64;
977    #[link_name = "llvm.hexagon.M2.mpyd.nac.hl.s1"]
978    fn hexagon_M2_mpyd_nac_hl_s1(_: i64, _: i32, _: i32) -> i64;
979    #[link_name = "llvm.hexagon.M2.mpyd.nac.lh.s0"]
980    fn hexagon_M2_mpyd_nac_lh_s0(_: i64, _: i32, _: i32) -> i64;
981    #[link_name = "llvm.hexagon.M2.mpyd.nac.lh.s1"]
982    fn hexagon_M2_mpyd_nac_lh_s1(_: i64, _: i32, _: i32) -> i64;
983    #[link_name = "llvm.hexagon.M2.mpyd.nac.ll.s0"]
984    fn hexagon_M2_mpyd_nac_ll_s0(_: i64, _: i32, _: i32) -> i64;
985    #[link_name = "llvm.hexagon.M2.mpyd.nac.ll.s1"]
986    fn hexagon_M2_mpyd_nac_ll_s1(_: i64, _: i32, _: i32) -> i64;
987    #[link_name = "llvm.hexagon.M2.mpyd.rnd.hh.s0"]
988    fn hexagon_M2_mpyd_rnd_hh_s0(_: i32, _: i32) -> i64;
989    #[link_name = "llvm.hexagon.M2.mpyd.rnd.hh.s1"]
990    fn hexagon_M2_mpyd_rnd_hh_s1(_: i32, _: i32) -> i64;
991    #[link_name = "llvm.hexagon.M2.mpyd.rnd.hl.s0"]
992    fn hexagon_M2_mpyd_rnd_hl_s0(_: i32, _: i32) -> i64;
993    #[link_name = "llvm.hexagon.M2.mpyd.rnd.hl.s1"]
994    fn hexagon_M2_mpyd_rnd_hl_s1(_: i32, _: i32) -> i64;
995    #[link_name = "llvm.hexagon.M2.mpyd.rnd.lh.s0"]
996    fn hexagon_M2_mpyd_rnd_lh_s0(_: i32, _: i32) -> i64;
997    #[link_name = "llvm.hexagon.M2.mpyd.rnd.lh.s1"]
998    fn hexagon_M2_mpyd_rnd_lh_s1(_: i32, _: i32) -> i64;
999    #[link_name = "llvm.hexagon.M2.mpyd.rnd.ll.s0"]
1000    fn hexagon_M2_mpyd_rnd_ll_s0(_: i32, _: i32) -> i64;
1001    #[link_name = "llvm.hexagon.M2.mpyd.rnd.ll.s1"]
1002    fn hexagon_M2_mpyd_rnd_ll_s1(_: i32, _: i32) -> i64;
1003    #[link_name = "llvm.hexagon.M2.mpyi"]
1004    fn hexagon_M2_mpyi(_: i32, _: i32) -> i32;
1005    #[link_name = "llvm.hexagon.M2.mpysmi"]
1006    fn hexagon_M2_mpysmi(_: i32, _: i32) -> i32;
1007    #[link_name = "llvm.hexagon.M2.mpysu.up"]
1008    fn hexagon_M2_mpysu_up(_: i32, _: i32) -> i32;
1009    #[link_name = "llvm.hexagon.M2.mpyu.acc.hh.s0"]
1010    fn hexagon_M2_mpyu_acc_hh_s0(_: i32, _: i32, _: i32) -> i32;
1011    #[link_name = "llvm.hexagon.M2.mpyu.acc.hh.s1"]
1012    fn hexagon_M2_mpyu_acc_hh_s1(_: i32, _: i32, _: i32) -> i32;
1013    #[link_name = "llvm.hexagon.M2.mpyu.acc.hl.s0"]
1014    fn hexagon_M2_mpyu_acc_hl_s0(_: i32, _: i32, _: i32) -> i32;
1015    #[link_name = "llvm.hexagon.M2.mpyu.acc.hl.s1"]
1016    fn hexagon_M2_mpyu_acc_hl_s1(_: i32, _: i32, _: i32) -> i32;
1017    #[link_name = "llvm.hexagon.M2.mpyu.acc.lh.s0"]
1018    fn hexagon_M2_mpyu_acc_lh_s0(_: i32, _: i32, _: i32) -> i32;
1019    #[link_name = "llvm.hexagon.M2.mpyu.acc.lh.s1"]
1020    fn hexagon_M2_mpyu_acc_lh_s1(_: i32, _: i32, _: i32) -> i32;
1021    #[link_name = "llvm.hexagon.M2.mpyu.acc.ll.s0"]
1022    fn hexagon_M2_mpyu_acc_ll_s0(_: i32, _: i32, _: i32) -> i32;
1023    #[link_name = "llvm.hexagon.M2.mpyu.acc.ll.s1"]
1024    fn hexagon_M2_mpyu_acc_ll_s1(_: i32, _: i32, _: i32) -> i32;
1025    #[link_name = "llvm.hexagon.M2.mpyu.hh.s0"]
1026    fn hexagon_M2_mpyu_hh_s0(_: i32, _: i32) -> i32;
1027    #[link_name = "llvm.hexagon.M2.mpyu.hh.s1"]
1028    fn hexagon_M2_mpyu_hh_s1(_: i32, _: i32) -> i32;
1029    #[link_name = "llvm.hexagon.M2.mpyu.hl.s0"]
1030    fn hexagon_M2_mpyu_hl_s0(_: i32, _: i32) -> i32;
1031    #[link_name = "llvm.hexagon.M2.mpyu.hl.s1"]
1032    fn hexagon_M2_mpyu_hl_s1(_: i32, _: i32) -> i32;
1033    #[link_name = "llvm.hexagon.M2.mpyu.lh.s0"]
1034    fn hexagon_M2_mpyu_lh_s0(_: i32, _: i32) -> i32;
1035    #[link_name = "llvm.hexagon.M2.mpyu.lh.s1"]
1036    fn hexagon_M2_mpyu_lh_s1(_: i32, _: i32) -> i32;
1037    #[link_name = "llvm.hexagon.M2.mpyu.ll.s0"]
1038    fn hexagon_M2_mpyu_ll_s0(_: i32, _: i32) -> i32;
1039    #[link_name = "llvm.hexagon.M2.mpyu.ll.s1"]
1040    fn hexagon_M2_mpyu_ll_s1(_: i32, _: i32) -> i32;
1041    #[link_name = "llvm.hexagon.M2.mpyu.nac.hh.s0"]
1042    fn hexagon_M2_mpyu_nac_hh_s0(_: i32, _: i32, _: i32) -> i32;
1043    #[link_name = "llvm.hexagon.M2.mpyu.nac.hh.s1"]
1044    fn hexagon_M2_mpyu_nac_hh_s1(_: i32, _: i32, _: i32) -> i32;
1045    #[link_name = "llvm.hexagon.M2.mpyu.nac.hl.s0"]
1046    fn hexagon_M2_mpyu_nac_hl_s0(_: i32, _: i32, _: i32) -> i32;
1047    #[link_name = "llvm.hexagon.M2.mpyu.nac.hl.s1"]
1048    fn hexagon_M2_mpyu_nac_hl_s1(_: i32, _: i32, _: i32) -> i32;
1049    #[link_name = "llvm.hexagon.M2.mpyu.nac.lh.s0"]
1050    fn hexagon_M2_mpyu_nac_lh_s0(_: i32, _: i32, _: i32) -> i32;
1051    #[link_name = "llvm.hexagon.M2.mpyu.nac.lh.s1"]
1052    fn hexagon_M2_mpyu_nac_lh_s1(_: i32, _: i32, _: i32) -> i32;
1053    #[link_name = "llvm.hexagon.M2.mpyu.nac.ll.s0"]
1054    fn hexagon_M2_mpyu_nac_ll_s0(_: i32, _: i32, _: i32) -> i32;
1055    #[link_name = "llvm.hexagon.M2.mpyu.nac.ll.s1"]
1056    fn hexagon_M2_mpyu_nac_ll_s1(_: i32, _: i32, _: i32) -> i32;
1057    #[link_name = "llvm.hexagon.M2.mpyu.up"]
1058    fn hexagon_M2_mpyu_up(_: i32, _: i32) -> i32;
1059    #[link_name = "llvm.hexagon.M2.mpyud.acc.hh.s0"]
1060    fn hexagon_M2_mpyud_acc_hh_s0(_: i64, _: i32, _: i32) -> i64;
1061    #[link_name = "llvm.hexagon.M2.mpyud.acc.hh.s1"]
1062    fn hexagon_M2_mpyud_acc_hh_s1(_: i64, _: i32, _: i32) -> i64;
1063    #[link_name = "llvm.hexagon.M2.mpyud.acc.hl.s0"]
1064    fn hexagon_M2_mpyud_acc_hl_s0(_: i64, _: i32, _: i32) -> i64;
1065    #[link_name = "llvm.hexagon.M2.mpyud.acc.hl.s1"]
1066    fn hexagon_M2_mpyud_acc_hl_s1(_: i64, _: i32, _: i32) -> i64;
1067    #[link_name = "llvm.hexagon.M2.mpyud.acc.lh.s0"]
1068    fn hexagon_M2_mpyud_acc_lh_s0(_: i64, _: i32, _: i32) -> i64;
1069    #[link_name = "llvm.hexagon.M2.mpyud.acc.lh.s1"]
1070    fn hexagon_M2_mpyud_acc_lh_s1(_: i64, _: i32, _: i32) -> i64;
1071    #[link_name = "llvm.hexagon.M2.mpyud.acc.ll.s0"]
1072    fn hexagon_M2_mpyud_acc_ll_s0(_: i64, _: i32, _: i32) -> i64;
1073    #[link_name = "llvm.hexagon.M2.mpyud.acc.ll.s1"]
1074    fn hexagon_M2_mpyud_acc_ll_s1(_: i64, _: i32, _: i32) -> i64;
1075    #[link_name = "llvm.hexagon.M2.mpyud.hh.s0"]
1076    fn hexagon_M2_mpyud_hh_s0(_: i32, _: i32) -> i64;
1077    #[link_name = "llvm.hexagon.M2.mpyud.hh.s1"]
1078    fn hexagon_M2_mpyud_hh_s1(_: i32, _: i32) -> i64;
1079    #[link_name = "llvm.hexagon.M2.mpyud.hl.s0"]
1080    fn hexagon_M2_mpyud_hl_s0(_: i32, _: i32) -> i64;
1081    #[link_name = "llvm.hexagon.M2.mpyud.hl.s1"]
1082    fn hexagon_M2_mpyud_hl_s1(_: i32, _: i32) -> i64;
1083    #[link_name = "llvm.hexagon.M2.mpyud.lh.s0"]
1084    fn hexagon_M2_mpyud_lh_s0(_: i32, _: i32) -> i64;
1085    #[link_name = "llvm.hexagon.M2.mpyud.lh.s1"]
1086    fn hexagon_M2_mpyud_lh_s1(_: i32, _: i32) -> i64;
1087    #[link_name = "llvm.hexagon.M2.mpyud.ll.s0"]
1088    fn hexagon_M2_mpyud_ll_s0(_: i32, _: i32) -> i64;
1089    #[link_name = "llvm.hexagon.M2.mpyud.ll.s1"]
1090    fn hexagon_M2_mpyud_ll_s1(_: i32, _: i32) -> i64;
1091    #[link_name = "llvm.hexagon.M2.mpyud.nac.hh.s0"]
1092    fn hexagon_M2_mpyud_nac_hh_s0(_: i64, _: i32, _: i32) -> i64;
1093    #[link_name = "llvm.hexagon.M2.mpyud.nac.hh.s1"]
1094    fn hexagon_M2_mpyud_nac_hh_s1(_: i64, _: i32, _: i32) -> i64;
1095    #[link_name = "llvm.hexagon.M2.mpyud.nac.hl.s0"]
1096    fn hexagon_M2_mpyud_nac_hl_s0(_: i64, _: i32, _: i32) -> i64;
1097    #[link_name = "llvm.hexagon.M2.mpyud.nac.hl.s1"]
1098    fn hexagon_M2_mpyud_nac_hl_s1(_: i64, _: i32, _: i32) -> i64;
1099    #[link_name = "llvm.hexagon.M2.mpyud.nac.lh.s0"]
1100    fn hexagon_M2_mpyud_nac_lh_s0(_: i64, _: i32, _: i32) -> i64;
1101    #[link_name = "llvm.hexagon.M2.mpyud.nac.lh.s1"]
1102    fn hexagon_M2_mpyud_nac_lh_s1(_: i64, _: i32, _: i32) -> i64;
1103    #[link_name = "llvm.hexagon.M2.mpyud.nac.ll.s0"]
1104    fn hexagon_M2_mpyud_nac_ll_s0(_: i64, _: i32, _: i32) -> i64;
1105    #[link_name = "llvm.hexagon.M2.mpyud.nac.ll.s1"]
1106    fn hexagon_M2_mpyud_nac_ll_s1(_: i64, _: i32, _: i32) -> i64;
1107    #[link_name = "llvm.hexagon.M2.mpyui"]
1108    fn hexagon_M2_mpyui(_: i32, _: i32) -> i32;
1109    #[link_name = "llvm.hexagon.M2.nacci"]
1110    fn hexagon_M2_nacci(_: i32, _: i32, _: i32) -> i32;
1111    #[link_name = "llvm.hexagon.M2.naccii"]
1112    fn hexagon_M2_naccii(_: i32, _: i32, _: i32) -> i32;
1113    #[link_name = "llvm.hexagon.M2.subacc"]
1114    fn hexagon_M2_subacc(_: i32, _: i32, _: i32) -> i32;
1115    #[link_name = "llvm.hexagon.M2.vabsdiffh"]
1116    fn hexagon_M2_vabsdiffh(_: i64, _: i64) -> i64;
1117    #[link_name = "llvm.hexagon.M2.vabsdiffw"]
1118    fn hexagon_M2_vabsdiffw(_: i64, _: i64) -> i64;
1119    #[link_name = "llvm.hexagon.M2.vcmac.s0.sat.i"]
1120    fn hexagon_M2_vcmac_s0_sat_i(_: i64, _: i64, _: i64) -> i64;
1121    #[link_name = "llvm.hexagon.M2.vcmac.s0.sat.r"]
1122    fn hexagon_M2_vcmac_s0_sat_r(_: i64, _: i64, _: i64) -> i64;
1123    #[link_name = "llvm.hexagon.M2.vcmpy.s0.sat.i"]
1124    fn hexagon_M2_vcmpy_s0_sat_i(_: i64, _: i64) -> i64;
1125    #[link_name = "llvm.hexagon.M2.vcmpy.s0.sat.r"]
1126    fn hexagon_M2_vcmpy_s0_sat_r(_: i64, _: i64) -> i64;
1127    #[link_name = "llvm.hexagon.M2.vcmpy.s1.sat.i"]
1128    fn hexagon_M2_vcmpy_s1_sat_i(_: i64, _: i64) -> i64;
1129    #[link_name = "llvm.hexagon.M2.vcmpy.s1.sat.r"]
1130    fn hexagon_M2_vcmpy_s1_sat_r(_: i64, _: i64) -> i64;
1131    #[link_name = "llvm.hexagon.M2.vdmacs.s0"]
1132    fn hexagon_M2_vdmacs_s0(_: i64, _: i64, _: i64) -> i64;
1133    #[link_name = "llvm.hexagon.M2.vdmacs.s1"]
1134    fn hexagon_M2_vdmacs_s1(_: i64, _: i64, _: i64) -> i64;
1135    #[link_name = "llvm.hexagon.M2.vdmpyrs.s0"]
1136    fn hexagon_M2_vdmpyrs_s0(_: i64, _: i64) -> i32;
1137    #[link_name = "llvm.hexagon.M2.vdmpyrs.s1"]
1138    fn hexagon_M2_vdmpyrs_s1(_: i64, _: i64) -> i32;
1139    #[link_name = "llvm.hexagon.M2.vdmpys.s0"]
1140    fn hexagon_M2_vdmpys_s0(_: i64, _: i64) -> i64;
1141    #[link_name = "llvm.hexagon.M2.vdmpys.s1"]
1142    fn hexagon_M2_vdmpys_s1(_: i64, _: i64) -> i64;
1143    #[link_name = "llvm.hexagon.M2.vmac2"]
1144    fn hexagon_M2_vmac2(_: i64, _: i32, _: i32) -> i64;
1145    #[link_name = "llvm.hexagon.M2.vmac2es"]
1146    fn hexagon_M2_vmac2es(_: i64, _: i64, _: i64) -> i64;
1147    #[link_name = "llvm.hexagon.M2.vmac2es.s0"]
1148    fn hexagon_M2_vmac2es_s0(_: i64, _: i64, _: i64) -> i64;
1149    #[link_name = "llvm.hexagon.M2.vmac2es.s1"]
1150    fn hexagon_M2_vmac2es_s1(_: i64, _: i64, _: i64) -> i64;
1151    #[link_name = "llvm.hexagon.M2.vmac2s.s0"]
1152    fn hexagon_M2_vmac2s_s0(_: i64, _: i32, _: i32) -> i64;
1153    #[link_name = "llvm.hexagon.M2.vmac2s.s1"]
1154    fn hexagon_M2_vmac2s_s1(_: i64, _: i32, _: i32) -> i64;
1155    #[link_name = "llvm.hexagon.M2.vmac2su.s0"]
1156    fn hexagon_M2_vmac2su_s0(_: i64, _: i32, _: i32) -> i64;
1157    #[link_name = "llvm.hexagon.M2.vmac2su.s1"]
1158    fn hexagon_M2_vmac2su_s1(_: i64, _: i32, _: i32) -> i64;
1159    #[link_name = "llvm.hexagon.M2.vmpy2es.s0"]
1160    fn hexagon_M2_vmpy2es_s0(_: i64, _: i64) -> i64;
1161    #[link_name = "llvm.hexagon.M2.vmpy2es.s1"]
1162    fn hexagon_M2_vmpy2es_s1(_: i64, _: i64) -> i64;
1163    #[link_name = "llvm.hexagon.M2.vmpy2s.s0"]
1164    fn hexagon_M2_vmpy2s_s0(_: i32, _: i32) -> i64;
1165    #[link_name = "llvm.hexagon.M2.vmpy2s.s0pack"]
1166    fn hexagon_M2_vmpy2s_s0pack(_: i32, _: i32) -> i32;
1167    #[link_name = "llvm.hexagon.M2.vmpy2s.s1"]
1168    fn hexagon_M2_vmpy2s_s1(_: i32, _: i32) -> i64;
1169    #[link_name = "llvm.hexagon.M2.vmpy2s.s1pack"]
1170    fn hexagon_M2_vmpy2s_s1pack(_: i32, _: i32) -> i32;
1171    #[link_name = "llvm.hexagon.M2.vmpy2su.s0"]
1172    fn hexagon_M2_vmpy2su_s0(_: i32, _: i32) -> i64;
1173    #[link_name = "llvm.hexagon.M2.vmpy2su.s1"]
1174    fn hexagon_M2_vmpy2su_s1(_: i32, _: i32) -> i64;
1175    #[link_name = "llvm.hexagon.M2.vraddh"]
1176    fn hexagon_M2_vraddh(_: i64, _: i64) -> i32;
1177    #[link_name = "llvm.hexagon.M2.vradduh"]
1178    fn hexagon_M2_vradduh(_: i64, _: i64) -> i32;
1179    #[link_name = "llvm.hexagon.M2.vrcmaci.s0"]
1180    fn hexagon_M2_vrcmaci_s0(_: i64, _: i64, _: i64) -> i64;
1181    #[link_name = "llvm.hexagon.M2.vrcmaci.s0c"]
1182    fn hexagon_M2_vrcmaci_s0c(_: i64, _: i64, _: i64) -> i64;
1183    #[link_name = "llvm.hexagon.M2.vrcmacr.s0"]
1184    fn hexagon_M2_vrcmacr_s0(_: i64, _: i64, _: i64) -> i64;
1185    #[link_name = "llvm.hexagon.M2.vrcmacr.s0c"]
1186    fn hexagon_M2_vrcmacr_s0c(_: i64, _: i64, _: i64) -> i64;
1187    #[link_name = "llvm.hexagon.M2.vrcmpyi.s0"]
1188    fn hexagon_M2_vrcmpyi_s0(_: i64, _: i64) -> i64;
1189    #[link_name = "llvm.hexagon.M2.vrcmpyi.s0c"]
1190    fn hexagon_M2_vrcmpyi_s0c(_: i64, _: i64) -> i64;
1191    #[link_name = "llvm.hexagon.M2.vrcmpyr.s0"]
1192    fn hexagon_M2_vrcmpyr_s0(_: i64, _: i64) -> i64;
1193    #[link_name = "llvm.hexagon.M2.vrcmpyr.s0c"]
1194    fn hexagon_M2_vrcmpyr_s0c(_: i64, _: i64) -> i64;
1195    #[link_name = "llvm.hexagon.M2.vrcmpys.acc.s1"]
1196    fn hexagon_M2_vrcmpys_acc_s1(_: i64, _: i64, _: i32) -> i64;
1197    #[link_name = "llvm.hexagon.M2.vrcmpys.s1"]
1198    fn hexagon_M2_vrcmpys_s1(_: i64, _: i32) -> i64;
1199    #[link_name = "llvm.hexagon.M2.vrcmpys.s1rp"]
1200    fn hexagon_M2_vrcmpys_s1rp(_: i64, _: i32) -> i32;
1201    #[link_name = "llvm.hexagon.M2.vrmac.s0"]
1202    fn hexagon_M2_vrmac_s0(_: i64, _: i64, _: i64) -> i64;
1203    #[link_name = "llvm.hexagon.M2.vrmpy.s0"]
1204    fn hexagon_M2_vrmpy_s0(_: i64, _: i64) -> i64;
1205    #[link_name = "llvm.hexagon.M2.xor.xacc"]
1206    fn hexagon_M2_xor_xacc(_: i32, _: i32, _: i32) -> i32;
1207    #[link_name = "llvm.hexagon.M4.and.and"]
1208    fn hexagon_M4_and_and(_: i32, _: i32, _: i32) -> i32;
1209    #[link_name = "llvm.hexagon.M4.and.andn"]
1210    fn hexagon_M4_and_andn(_: i32, _: i32, _: i32) -> i32;
1211    #[link_name = "llvm.hexagon.M4.and.or"]
1212    fn hexagon_M4_and_or(_: i32, _: i32, _: i32) -> i32;
1213    #[link_name = "llvm.hexagon.M4.and.xor"]
1214    fn hexagon_M4_and_xor(_: i32, _: i32, _: i32) -> i32;
1215    #[link_name = "llvm.hexagon.M4.cmpyi.wh"]
1216    fn hexagon_M4_cmpyi_wh(_: i64, _: i32) -> i32;
1217    #[link_name = "llvm.hexagon.M4.cmpyi.whc"]
1218    fn hexagon_M4_cmpyi_whc(_: i64, _: i32) -> i32;
1219    #[link_name = "llvm.hexagon.M4.cmpyr.wh"]
1220    fn hexagon_M4_cmpyr_wh(_: i64, _: i32) -> i32;
1221    #[link_name = "llvm.hexagon.M4.cmpyr.whc"]
1222    fn hexagon_M4_cmpyr_whc(_: i64, _: i32) -> i32;
1223    #[link_name = "llvm.hexagon.M4.mac.up.s1.sat"]
1224    fn hexagon_M4_mac_up_s1_sat(_: i32, _: i32, _: i32) -> i32;
1225    #[link_name = "llvm.hexagon.M4.mpyri.addi"]
1226    fn hexagon_M4_mpyri_addi(_: i32, _: i32, _: i32) -> i32;
1227    #[link_name = "llvm.hexagon.M4.mpyri.addr"]
1228    fn hexagon_M4_mpyri_addr(_: i32, _: i32, _: i32) -> i32;
1229    #[link_name = "llvm.hexagon.M4.mpyri.addr.u2"]
1230    fn hexagon_M4_mpyri_addr_u2(_: i32, _: i32, _: i32) -> i32;
1231    #[link_name = "llvm.hexagon.M4.mpyrr.addi"]
1232    fn hexagon_M4_mpyrr_addi(_: i32, _: i32, _: i32) -> i32;
1233    #[link_name = "llvm.hexagon.M4.mpyrr.addr"]
1234    fn hexagon_M4_mpyrr_addr(_: i32, _: i32, _: i32) -> i32;
1235    #[link_name = "llvm.hexagon.M4.nac.up.s1.sat"]
1236    fn hexagon_M4_nac_up_s1_sat(_: i32, _: i32, _: i32) -> i32;
1237    #[link_name = "llvm.hexagon.M4.or.and"]
1238    fn hexagon_M4_or_and(_: i32, _: i32, _: i32) -> i32;
1239    #[link_name = "llvm.hexagon.M4.or.andn"]
1240    fn hexagon_M4_or_andn(_: i32, _: i32, _: i32) -> i32;
1241    #[link_name = "llvm.hexagon.M4.or.or"]
1242    fn hexagon_M4_or_or(_: i32, _: i32, _: i32) -> i32;
1243    #[link_name = "llvm.hexagon.M4.or.xor"]
1244    fn hexagon_M4_or_xor(_: i32, _: i32, _: i32) -> i32;
1245    #[link_name = "llvm.hexagon.M4.pmpyw"]
1246    fn hexagon_M4_pmpyw(_: i32, _: i32) -> i64;
1247    #[link_name = "llvm.hexagon.M4.pmpyw.acc"]
1248    fn hexagon_M4_pmpyw_acc(_: i64, _: i32, _: i32) -> i64;
1249    #[link_name = "llvm.hexagon.M4.vpmpyh"]
1250    fn hexagon_M4_vpmpyh(_: i32, _: i32) -> i64;
1251    #[link_name = "llvm.hexagon.M4.vpmpyh.acc"]
1252    fn hexagon_M4_vpmpyh_acc(_: i64, _: i32, _: i32) -> i64;
1253    #[link_name = "llvm.hexagon.M4.vrmpyeh.acc.s0"]
1254    fn hexagon_M4_vrmpyeh_acc_s0(_: i64, _: i64, _: i64) -> i64;
1255    #[link_name = "llvm.hexagon.M4.vrmpyeh.acc.s1"]
1256    fn hexagon_M4_vrmpyeh_acc_s1(_: i64, _: i64, _: i64) -> i64;
1257    #[link_name = "llvm.hexagon.M4.vrmpyeh.s0"]
1258    fn hexagon_M4_vrmpyeh_s0(_: i64, _: i64) -> i64;
1259    #[link_name = "llvm.hexagon.M4.vrmpyeh.s1"]
1260    fn hexagon_M4_vrmpyeh_s1(_: i64, _: i64) -> i64;
1261    #[link_name = "llvm.hexagon.M4.vrmpyoh.acc.s0"]
1262    fn hexagon_M4_vrmpyoh_acc_s0(_: i64, _: i64, _: i64) -> i64;
1263    #[link_name = "llvm.hexagon.M4.vrmpyoh.acc.s1"]
1264    fn hexagon_M4_vrmpyoh_acc_s1(_: i64, _: i64, _: i64) -> i64;
1265    #[link_name = "llvm.hexagon.M4.vrmpyoh.s0"]
1266    fn hexagon_M4_vrmpyoh_s0(_: i64, _: i64) -> i64;
1267    #[link_name = "llvm.hexagon.M4.vrmpyoh.s1"]
1268    fn hexagon_M4_vrmpyoh_s1(_: i64, _: i64) -> i64;
1269    #[link_name = "llvm.hexagon.M4.xor.and"]
1270    fn hexagon_M4_xor_and(_: i32, _: i32, _: i32) -> i32;
1271    #[link_name = "llvm.hexagon.M4.xor.andn"]
1272    fn hexagon_M4_xor_andn(_: i32, _: i32, _: i32) -> i32;
1273    #[link_name = "llvm.hexagon.M4.xor.or"]
1274    fn hexagon_M4_xor_or(_: i32, _: i32, _: i32) -> i32;
1275    #[link_name = "llvm.hexagon.M4.xor.xacc"]
1276    fn hexagon_M4_xor_xacc(_: i64, _: i64, _: i64) -> i64;
1277    #[link_name = "llvm.hexagon.M5.vdmacbsu"]
1278    fn hexagon_M5_vdmacbsu(_: i64, _: i64, _: i64) -> i64;
1279    #[link_name = "llvm.hexagon.M5.vdmpybsu"]
1280    fn hexagon_M5_vdmpybsu(_: i64, _: i64) -> i64;
1281    #[link_name = "llvm.hexagon.M5.vmacbsu"]
1282    fn hexagon_M5_vmacbsu(_: i64, _: i32, _: i32) -> i64;
1283    #[link_name = "llvm.hexagon.M5.vmacbuu"]
1284    fn hexagon_M5_vmacbuu(_: i64, _: i32, _: i32) -> i64;
1285    #[link_name = "llvm.hexagon.M5.vmpybsu"]
1286    fn hexagon_M5_vmpybsu(_: i32, _: i32) -> i64;
1287    #[link_name = "llvm.hexagon.M5.vmpybuu"]
1288    fn hexagon_M5_vmpybuu(_: i32, _: i32) -> i64;
1289    #[link_name = "llvm.hexagon.M5.vrmacbsu"]
1290    fn hexagon_M5_vrmacbsu(_: i64, _: i64, _: i64) -> i64;
1291    #[link_name = "llvm.hexagon.M5.vrmacbuu"]
1292    fn hexagon_M5_vrmacbuu(_: i64, _: i64, _: i64) -> i64;
1293    #[link_name = "llvm.hexagon.M5.vrmpybsu"]
1294    fn hexagon_M5_vrmpybsu(_: i64, _: i64) -> i64;
1295    #[link_name = "llvm.hexagon.M5.vrmpybuu"]
1296    fn hexagon_M5_vrmpybuu(_: i64, _: i64) -> i64;
1297    #[link_name = "llvm.hexagon.S2.addasl.rrri"]
1298    fn hexagon_S2_addasl_rrri(_: i32, _: i32, _: i32) -> i32;
1299    #[link_name = "llvm.hexagon.S2.asl.i.p"]
1300    fn hexagon_S2_asl_i_p(_: i64, _: i32) -> i64;
1301    #[link_name = "llvm.hexagon.S2.asl.i.p.acc"]
1302    fn hexagon_S2_asl_i_p_acc(_: i64, _: i64, _: i32) -> i64;
1303    #[link_name = "llvm.hexagon.S2.asl.i.p.and"]
1304    fn hexagon_S2_asl_i_p_and(_: i64, _: i64, _: i32) -> i64;
1305    #[link_name = "llvm.hexagon.S2.asl.i.p.nac"]
1306    fn hexagon_S2_asl_i_p_nac(_: i64, _: i64, _: i32) -> i64;
1307    #[link_name = "llvm.hexagon.S2.asl.i.p.or"]
1308    fn hexagon_S2_asl_i_p_or(_: i64, _: i64, _: i32) -> i64;
1309    #[link_name = "llvm.hexagon.S2.asl.i.p.xacc"]
1310    fn hexagon_S2_asl_i_p_xacc(_: i64, _: i64, _: i32) -> i64;
1311    #[link_name = "llvm.hexagon.S2.asl.i.r"]
1312    fn hexagon_S2_asl_i_r(_: i32, _: i32) -> i32;
1313    #[link_name = "llvm.hexagon.S2.asl.i.r.acc"]
1314    fn hexagon_S2_asl_i_r_acc(_: i32, _: i32, _: i32) -> i32;
1315    #[link_name = "llvm.hexagon.S2.asl.i.r.and"]
1316    fn hexagon_S2_asl_i_r_and(_: i32, _: i32, _: i32) -> i32;
1317    #[link_name = "llvm.hexagon.S2.asl.i.r.nac"]
1318    fn hexagon_S2_asl_i_r_nac(_: i32, _: i32, _: i32) -> i32;
1319    #[link_name = "llvm.hexagon.S2.asl.i.r.or"]
1320    fn hexagon_S2_asl_i_r_or(_: i32, _: i32, _: i32) -> i32;
1321    #[link_name = "llvm.hexagon.S2.asl.i.r.sat"]
1322    fn hexagon_S2_asl_i_r_sat(_: i32, _: i32) -> i32;
1323    #[link_name = "llvm.hexagon.S2.asl.i.r.xacc"]
1324    fn hexagon_S2_asl_i_r_xacc(_: i32, _: i32, _: i32) -> i32;
1325    #[link_name = "llvm.hexagon.S2.asl.i.vh"]
1326    fn hexagon_S2_asl_i_vh(_: i64, _: i32) -> i64;
1327    #[link_name = "llvm.hexagon.S2.asl.i.vw"]
1328    fn hexagon_S2_asl_i_vw(_: i64, _: i32) -> i64;
1329    #[link_name = "llvm.hexagon.S2.asl.r.p"]
1330    fn hexagon_S2_asl_r_p(_: i64, _: i32) -> i64;
1331    #[link_name = "llvm.hexagon.S2.asl.r.p.acc"]
1332    fn hexagon_S2_asl_r_p_acc(_: i64, _: i64, _: i32) -> i64;
1333    #[link_name = "llvm.hexagon.S2.asl.r.p.and"]
1334    fn hexagon_S2_asl_r_p_and(_: i64, _: i64, _: i32) -> i64;
1335    #[link_name = "llvm.hexagon.S2.asl.r.p.nac"]
1336    fn hexagon_S2_asl_r_p_nac(_: i64, _: i64, _: i32) -> i64;
1337    #[link_name = "llvm.hexagon.S2.asl.r.p.or"]
1338    fn hexagon_S2_asl_r_p_or(_: i64, _: i64, _: i32) -> i64;
1339    #[link_name = "llvm.hexagon.S2.asl.r.p.xor"]
1340    fn hexagon_S2_asl_r_p_xor(_: i64, _: i64, _: i32) -> i64;
1341    #[link_name = "llvm.hexagon.S2.asl.r.r"]
1342    fn hexagon_S2_asl_r_r(_: i32, _: i32) -> i32;
1343    #[link_name = "llvm.hexagon.S2.asl.r.r.acc"]
1344    fn hexagon_S2_asl_r_r_acc(_: i32, _: i32, _: i32) -> i32;
1345    #[link_name = "llvm.hexagon.S2.asl.r.r.and"]
1346    fn hexagon_S2_asl_r_r_and(_: i32, _: i32, _: i32) -> i32;
1347    #[link_name = "llvm.hexagon.S2.asl.r.r.nac"]
1348    fn hexagon_S2_asl_r_r_nac(_: i32, _: i32, _: i32) -> i32;
1349    #[link_name = "llvm.hexagon.S2.asl.r.r.or"]
1350    fn hexagon_S2_asl_r_r_or(_: i32, _: i32, _: i32) -> i32;
1351    #[link_name = "llvm.hexagon.S2.asl.r.r.sat"]
1352    fn hexagon_S2_asl_r_r_sat(_: i32, _: i32) -> i32;
1353    #[link_name = "llvm.hexagon.S2.asl.r.vh"]
1354    fn hexagon_S2_asl_r_vh(_: i64, _: i32) -> i64;
1355    #[link_name = "llvm.hexagon.S2.asl.r.vw"]
1356    fn hexagon_S2_asl_r_vw(_: i64, _: i32) -> i64;
1357    #[link_name = "llvm.hexagon.S2.asr.i.p"]
1358    fn hexagon_S2_asr_i_p(_: i64, _: i32) -> i64;
1359    #[link_name = "llvm.hexagon.S2.asr.i.p.acc"]
1360    fn hexagon_S2_asr_i_p_acc(_: i64, _: i64, _: i32) -> i64;
1361    #[link_name = "llvm.hexagon.S2.asr.i.p.and"]
1362    fn hexagon_S2_asr_i_p_and(_: i64, _: i64, _: i32) -> i64;
1363    #[link_name = "llvm.hexagon.S2.asr.i.p.nac"]
1364    fn hexagon_S2_asr_i_p_nac(_: i64, _: i64, _: i32) -> i64;
1365    #[link_name = "llvm.hexagon.S2.asr.i.p.or"]
1366    fn hexagon_S2_asr_i_p_or(_: i64, _: i64, _: i32) -> i64;
1367    #[link_name = "llvm.hexagon.S2.asr.i.p.rnd"]
1368    fn hexagon_S2_asr_i_p_rnd(_: i64, _: i32) -> i64;
1369    #[link_name = "llvm.hexagon.S2.asr.i.p.rnd.goodsyntax"]
1370    fn hexagon_S2_asr_i_p_rnd_goodsyntax(_: i64, _: i32) -> i64;
1371    #[link_name = "llvm.hexagon.S2.asr.i.r"]
1372    fn hexagon_S2_asr_i_r(_: i32, _: i32) -> i32;
1373    #[link_name = "llvm.hexagon.S2.asr.i.r.acc"]
1374    fn hexagon_S2_asr_i_r_acc(_: i32, _: i32, _: i32) -> i32;
1375    #[link_name = "llvm.hexagon.S2.asr.i.r.and"]
1376    fn hexagon_S2_asr_i_r_and(_: i32, _: i32, _: i32) -> i32;
1377    #[link_name = "llvm.hexagon.S2.asr.i.r.nac"]
1378    fn hexagon_S2_asr_i_r_nac(_: i32, _: i32, _: i32) -> i32;
1379    #[link_name = "llvm.hexagon.S2.asr.i.r.or"]
1380    fn hexagon_S2_asr_i_r_or(_: i32, _: i32, _: i32) -> i32;
1381    #[link_name = "llvm.hexagon.S2.asr.i.r.rnd"]
1382    fn hexagon_S2_asr_i_r_rnd(_: i32, _: i32) -> i32;
1383    #[link_name = "llvm.hexagon.S2.asr.i.r.rnd.goodsyntax"]
1384    fn hexagon_S2_asr_i_r_rnd_goodsyntax(_: i32, _: i32) -> i32;
1385    #[link_name = "llvm.hexagon.S2.asr.i.svw.trun"]
1386    fn hexagon_S2_asr_i_svw_trun(_: i64, _: i32) -> i32;
1387    #[link_name = "llvm.hexagon.S2.asr.i.vh"]
1388    fn hexagon_S2_asr_i_vh(_: i64, _: i32) -> i64;
1389    #[link_name = "llvm.hexagon.S2.asr.i.vw"]
1390    fn hexagon_S2_asr_i_vw(_: i64, _: i32) -> i64;
1391    #[link_name = "llvm.hexagon.S2.asr.r.p"]
1392    fn hexagon_S2_asr_r_p(_: i64, _: i32) -> i64;
1393    #[link_name = "llvm.hexagon.S2.asr.r.p.acc"]
1394    fn hexagon_S2_asr_r_p_acc(_: i64, _: i64, _: i32) -> i64;
1395    #[link_name = "llvm.hexagon.S2.asr.r.p.and"]
1396    fn hexagon_S2_asr_r_p_and(_: i64, _: i64, _: i32) -> i64;
1397    #[link_name = "llvm.hexagon.S2.asr.r.p.nac"]
1398    fn hexagon_S2_asr_r_p_nac(_: i64, _: i64, _: i32) -> i64;
1399    #[link_name = "llvm.hexagon.S2.asr.r.p.or"]
1400    fn hexagon_S2_asr_r_p_or(_: i64, _: i64, _: i32) -> i64;
1401    #[link_name = "llvm.hexagon.S2.asr.r.p.xor"]
1402    fn hexagon_S2_asr_r_p_xor(_: i64, _: i64, _: i32) -> i64;
1403    #[link_name = "llvm.hexagon.S2.asr.r.r"]
1404    fn hexagon_S2_asr_r_r(_: i32, _: i32) -> i32;
1405    #[link_name = "llvm.hexagon.S2.asr.r.r.acc"]
1406    fn hexagon_S2_asr_r_r_acc(_: i32, _: i32, _: i32) -> i32;
1407    #[link_name = "llvm.hexagon.S2.asr.r.r.and"]
1408    fn hexagon_S2_asr_r_r_and(_: i32, _: i32, _: i32) -> i32;
1409    #[link_name = "llvm.hexagon.S2.asr.r.r.nac"]
1410    fn hexagon_S2_asr_r_r_nac(_: i32, _: i32, _: i32) -> i32;
1411    #[link_name = "llvm.hexagon.S2.asr.r.r.or"]
1412    fn hexagon_S2_asr_r_r_or(_: i32, _: i32, _: i32) -> i32;
1413    #[link_name = "llvm.hexagon.S2.asr.r.r.sat"]
1414    fn hexagon_S2_asr_r_r_sat(_: i32, _: i32) -> i32;
1415    #[link_name = "llvm.hexagon.S2.asr.r.svw.trun"]
1416    fn hexagon_S2_asr_r_svw_trun(_: i64, _: i32) -> i32;
1417    #[link_name = "llvm.hexagon.S2.asr.r.vh"]
1418    fn hexagon_S2_asr_r_vh(_: i64, _: i32) -> i64;
1419    #[link_name = "llvm.hexagon.S2.asr.r.vw"]
1420    fn hexagon_S2_asr_r_vw(_: i64, _: i32) -> i64;
1421    #[link_name = "llvm.hexagon.S2.brev"]
1422    fn hexagon_S2_brev(_: i32) -> i32;
1423    #[link_name = "llvm.hexagon.S2.brevp"]
1424    fn hexagon_S2_brevp(_: i64) -> i64;
1425    #[link_name = "llvm.hexagon.S2.cl0"]
1426    fn hexagon_S2_cl0(_: i32) -> i32;
1427    #[link_name = "llvm.hexagon.S2.cl0p"]
1428    fn hexagon_S2_cl0p(_: i64) -> i32;
1429    #[link_name = "llvm.hexagon.S2.cl1"]
1430    fn hexagon_S2_cl1(_: i32) -> i32;
1431    #[link_name = "llvm.hexagon.S2.cl1p"]
1432    fn hexagon_S2_cl1p(_: i64) -> i32;
1433    #[link_name = "llvm.hexagon.S2.clb"]
1434    fn hexagon_S2_clb(_: i32) -> i32;
1435    #[link_name = "llvm.hexagon.S2.clbnorm"]
1436    fn hexagon_S2_clbnorm(_: i32) -> i32;
1437    #[link_name = "llvm.hexagon.S2.clbp"]
1438    fn hexagon_S2_clbp(_: i64) -> i32;
1439    #[link_name = "llvm.hexagon.S2.clrbit.i"]
1440    fn hexagon_S2_clrbit_i(_: i32, _: i32) -> i32;
1441    #[link_name = "llvm.hexagon.S2.clrbit.r"]
1442    fn hexagon_S2_clrbit_r(_: i32, _: i32) -> i32;
1443    #[link_name = "llvm.hexagon.S2.ct0"]
1444    fn hexagon_S2_ct0(_: i32) -> i32;
1445    #[link_name = "llvm.hexagon.S2.ct0p"]
1446    fn hexagon_S2_ct0p(_: i64) -> i32;
1447    #[link_name = "llvm.hexagon.S2.ct1"]
1448    fn hexagon_S2_ct1(_: i32) -> i32;
1449    #[link_name = "llvm.hexagon.S2.ct1p"]
1450    fn hexagon_S2_ct1p(_: i64) -> i32;
1451    #[link_name = "llvm.hexagon.S2.deinterleave"]
1452    fn hexagon_S2_deinterleave(_: i64) -> i64;
1453    #[link_name = "llvm.hexagon.S2.extractu"]
1454    fn hexagon_S2_extractu(_: i32, _: i32, _: i32) -> i32;
1455    #[link_name = "llvm.hexagon.S2.extractu.rp"]
1456    fn hexagon_S2_extractu_rp(_: i32, _: i64) -> i32;
1457    #[link_name = "llvm.hexagon.S2.extractup"]
1458    fn hexagon_S2_extractup(_: i64, _: i32, _: i32) -> i64;
1459    #[link_name = "llvm.hexagon.S2.extractup.rp"]
1460    fn hexagon_S2_extractup_rp(_: i64, _: i64) -> i64;
1461    #[link_name = "llvm.hexagon.S2.insert"]
1462    fn hexagon_S2_insert(_: i32, _: i32, _: i32, _: i32) -> i32;
1463    #[link_name = "llvm.hexagon.S2.insert.rp"]
1464    fn hexagon_S2_insert_rp(_: i32, _: i32, _: i64) -> i32;
1465    #[link_name = "llvm.hexagon.S2.insertp"]
1466    fn hexagon_S2_insertp(_: i64, _: i64, _: i32, _: i32) -> i64;
1467    #[link_name = "llvm.hexagon.S2.insertp.rp"]
1468    fn hexagon_S2_insertp_rp(_: i64, _: i64, _: i64) -> i64;
1469    #[link_name = "llvm.hexagon.S2.interleave"]
1470    fn hexagon_S2_interleave(_: i64) -> i64;
1471    #[link_name = "llvm.hexagon.S2.lfsp"]
1472    fn hexagon_S2_lfsp(_: i64, _: i64) -> i64;
1473    #[link_name = "llvm.hexagon.S2.lsl.r.p"]
1474    fn hexagon_S2_lsl_r_p(_: i64, _: i32) -> i64;
1475    #[link_name = "llvm.hexagon.S2.lsl.r.p.acc"]
1476    fn hexagon_S2_lsl_r_p_acc(_: i64, _: i64, _: i32) -> i64;
1477    #[link_name = "llvm.hexagon.S2.lsl.r.p.and"]
1478    fn hexagon_S2_lsl_r_p_and(_: i64, _: i64, _: i32) -> i64;
1479    #[link_name = "llvm.hexagon.S2.lsl.r.p.nac"]
1480    fn hexagon_S2_lsl_r_p_nac(_: i64, _: i64, _: i32) -> i64;
1481    #[link_name = "llvm.hexagon.S2.lsl.r.p.or"]
1482    fn hexagon_S2_lsl_r_p_or(_: i64, _: i64, _: i32) -> i64;
1483    #[link_name = "llvm.hexagon.S2.lsl.r.p.xor"]
1484    fn hexagon_S2_lsl_r_p_xor(_: i64, _: i64, _: i32) -> i64;
1485    #[link_name = "llvm.hexagon.S2.lsl.r.r"]
1486    fn hexagon_S2_lsl_r_r(_: i32, _: i32) -> i32;
1487    #[link_name = "llvm.hexagon.S2.lsl.r.r.acc"]
1488    fn hexagon_S2_lsl_r_r_acc(_: i32, _: i32, _: i32) -> i32;
1489    #[link_name = "llvm.hexagon.S2.lsl.r.r.and"]
1490    fn hexagon_S2_lsl_r_r_and(_: i32, _: i32, _: i32) -> i32;
1491    #[link_name = "llvm.hexagon.S2.lsl.r.r.nac"]
1492    fn hexagon_S2_lsl_r_r_nac(_: i32, _: i32, _: i32) -> i32;
1493    #[link_name = "llvm.hexagon.S2.lsl.r.r.or"]
1494    fn hexagon_S2_lsl_r_r_or(_: i32, _: i32, _: i32) -> i32;
1495    #[link_name = "llvm.hexagon.S2.lsl.r.vh"]
1496    fn hexagon_S2_lsl_r_vh(_: i64, _: i32) -> i64;
1497    #[link_name = "llvm.hexagon.S2.lsl.r.vw"]
1498    fn hexagon_S2_lsl_r_vw(_: i64, _: i32) -> i64;
1499    #[link_name = "llvm.hexagon.S2.lsr.i.p"]
1500    fn hexagon_S2_lsr_i_p(_: i64, _: i32) -> i64;
1501    #[link_name = "llvm.hexagon.S2.lsr.i.p.acc"]
1502    fn hexagon_S2_lsr_i_p_acc(_: i64, _: i64, _: i32) -> i64;
1503    #[link_name = "llvm.hexagon.S2.lsr.i.p.and"]
1504    fn hexagon_S2_lsr_i_p_and(_: i64, _: i64, _: i32) -> i64;
1505    #[link_name = "llvm.hexagon.S2.lsr.i.p.nac"]
1506    fn hexagon_S2_lsr_i_p_nac(_: i64, _: i64, _: i32) -> i64;
1507    #[link_name = "llvm.hexagon.S2.lsr.i.p.or"]
1508    fn hexagon_S2_lsr_i_p_or(_: i64, _: i64, _: i32) -> i64;
1509    #[link_name = "llvm.hexagon.S2.lsr.i.p.xacc"]
1510    fn hexagon_S2_lsr_i_p_xacc(_: i64, _: i64, _: i32) -> i64;
1511    #[link_name = "llvm.hexagon.S2.lsr.i.r"]
1512    fn hexagon_S2_lsr_i_r(_: i32, _: i32) -> i32;
1513    #[link_name = "llvm.hexagon.S2.lsr.i.r.acc"]
1514    fn hexagon_S2_lsr_i_r_acc(_: i32, _: i32, _: i32) -> i32;
1515    #[link_name = "llvm.hexagon.S2.lsr.i.r.and"]
1516    fn hexagon_S2_lsr_i_r_and(_: i32, _: i32, _: i32) -> i32;
1517    #[link_name = "llvm.hexagon.S2.lsr.i.r.nac"]
1518    fn hexagon_S2_lsr_i_r_nac(_: i32, _: i32, _: i32) -> i32;
1519    #[link_name = "llvm.hexagon.S2.lsr.i.r.or"]
1520    fn hexagon_S2_lsr_i_r_or(_: i32, _: i32, _: i32) -> i32;
1521    #[link_name = "llvm.hexagon.S2.lsr.i.r.xacc"]
1522    fn hexagon_S2_lsr_i_r_xacc(_: i32, _: i32, _: i32) -> i32;
1523    #[link_name = "llvm.hexagon.S2.lsr.i.vh"]
1524    fn hexagon_S2_lsr_i_vh(_: i64, _: i32) -> i64;
1525    #[link_name = "llvm.hexagon.S2.lsr.i.vw"]
1526    fn hexagon_S2_lsr_i_vw(_: i64, _: i32) -> i64;
1527    #[link_name = "llvm.hexagon.S2.lsr.r.p"]
1528    fn hexagon_S2_lsr_r_p(_: i64, _: i32) -> i64;
1529    #[link_name = "llvm.hexagon.S2.lsr.r.p.acc"]
1530    fn hexagon_S2_lsr_r_p_acc(_: i64, _: i64, _: i32) -> i64;
1531    #[link_name = "llvm.hexagon.S2.lsr.r.p.and"]
1532    fn hexagon_S2_lsr_r_p_and(_: i64, _: i64, _: i32) -> i64;
1533    #[link_name = "llvm.hexagon.S2.lsr.r.p.nac"]
1534    fn hexagon_S2_lsr_r_p_nac(_: i64, _: i64, _: i32) -> i64;
1535    #[link_name = "llvm.hexagon.S2.lsr.r.p.or"]
1536    fn hexagon_S2_lsr_r_p_or(_: i64, _: i64, _: i32) -> i64;
1537    #[link_name = "llvm.hexagon.S2.lsr.r.p.xor"]
1538    fn hexagon_S2_lsr_r_p_xor(_: i64, _: i64, _: i32) -> i64;
1539    #[link_name = "llvm.hexagon.S2.lsr.r.r"]
1540    fn hexagon_S2_lsr_r_r(_: i32, _: i32) -> i32;
1541    #[link_name = "llvm.hexagon.S2.lsr.r.r.acc"]
1542    fn hexagon_S2_lsr_r_r_acc(_: i32, _: i32, _: i32) -> i32;
1543    #[link_name = "llvm.hexagon.S2.lsr.r.r.and"]
1544    fn hexagon_S2_lsr_r_r_and(_: i32, _: i32, _: i32) -> i32;
1545    #[link_name = "llvm.hexagon.S2.lsr.r.r.nac"]
1546    fn hexagon_S2_lsr_r_r_nac(_: i32, _: i32, _: i32) -> i32;
1547    #[link_name = "llvm.hexagon.S2.lsr.r.r.or"]
1548    fn hexagon_S2_lsr_r_r_or(_: i32, _: i32, _: i32) -> i32;
1549    #[link_name = "llvm.hexagon.S2.lsr.r.vh"]
1550    fn hexagon_S2_lsr_r_vh(_: i64, _: i32) -> i64;
1551    #[link_name = "llvm.hexagon.S2.lsr.r.vw"]
1552    fn hexagon_S2_lsr_r_vw(_: i64, _: i32) -> i64;
1553    #[link_name = "llvm.hexagon.S2.packhl"]
1554    fn hexagon_S2_packhl(_: i32, _: i32) -> i64;
1555    #[link_name = "llvm.hexagon.S2.parityp"]
1556    fn hexagon_S2_parityp(_: i64, _: i64) -> i32;
1557    #[link_name = "llvm.hexagon.S2.setbit.i"]
1558    fn hexagon_S2_setbit_i(_: i32, _: i32) -> i32;
1559    #[link_name = "llvm.hexagon.S2.setbit.r"]
1560    fn hexagon_S2_setbit_r(_: i32, _: i32) -> i32;
1561    #[link_name = "llvm.hexagon.S2.shuffeb"]
1562    fn hexagon_S2_shuffeb(_: i64, _: i64) -> i64;
1563    #[link_name = "llvm.hexagon.S2.shuffeh"]
1564    fn hexagon_S2_shuffeh(_: i64, _: i64) -> i64;
1565    #[link_name = "llvm.hexagon.S2.shuffob"]
1566    fn hexagon_S2_shuffob(_: i64, _: i64) -> i64;
1567    #[link_name = "llvm.hexagon.S2.shuffoh"]
1568    fn hexagon_S2_shuffoh(_: i64, _: i64) -> i64;
1569    #[link_name = "llvm.hexagon.S2.svsathb"]
1570    fn hexagon_S2_svsathb(_: i32) -> i32;
1571    #[link_name = "llvm.hexagon.S2.svsathub"]
1572    fn hexagon_S2_svsathub(_: i32) -> i32;
1573    #[link_name = "llvm.hexagon.S2.tableidxb.goodsyntax"]
1574    fn hexagon_S2_tableidxb_goodsyntax(_: i32, _: i32, _: i32, _: i32) -> i32;
1575    #[link_name = "llvm.hexagon.S2.tableidxd.goodsyntax"]
1576    fn hexagon_S2_tableidxd_goodsyntax(_: i32, _: i32, _: i32, _: i32) -> i32;
1577    #[link_name = "llvm.hexagon.S2.tableidxh.goodsyntax"]
1578    fn hexagon_S2_tableidxh_goodsyntax(_: i32, _: i32, _: i32, _: i32) -> i32;
1579    #[link_name = "llvm.hexagon.S2.tableidxw.goodsyntax"]
1580    fn hexagon_S2_tableidxw_goodsyntax(_: i32, _: i32, _: i32, _: i32) -> i32;
1581    #[link_name = "llvm.hexagon.S2.togglebit.i"]
1582    fn hexagon_S2_togglebit_i(_: i32, _: i32) -> i32;
1583    #[link_name = "llvm.hexagon.S2.togglebit.r"]
1584    fn hexagon_S2_togglebit_r(_: i32, _: i32) -> i32;
1585    #[link_name = "llvm.hexagon.S2.tstbit.i"]
1586    fn hexagon_S2_tstbit_i(_: i32, _: i32) -> i32;
1587    #[link_name = "llvm.hexagon.S2.tstbit.r"]
1588    fn hexagon_S2_tstbit_r(_: i32, _: i32) -> i32;
1589    #[link_name = "llvm.hexagon.S2.valignib"]
1590    fn hexagon_S2_valignib(_: i64, _: i64, _: i32) -> i64;
1591    #[link_name = "llvm.hexagon.S2.valignrb"]
1592    fn hexagon_S2_valignrb(_: i64, _: i64, _: i32) -> i64;
1593    #[link_name = "llvm.hexagon.S2.vcnegh"]
1594    fn hexagon_S2_vcnegh(_: i64, _: i32) -> i64;
1595    #[link_name = "llvm.hexagon.S2.vcrotate"]
1596    fn hexagon_S2_vcrotate(_: i64, _: i32) -> i64;
1597    #[link_name = "llvm.hexagon.S2.vrcnegh"]
1598    fn hexagon_S2_vrcnegh(_: i64, _: i64, _: i32) -> i64;
1599    #[link_name = "llvm.hexagon.S2.vrndpackwh"]
1600    fn hexagon_S2_vrndpackwh(_: i64) -> i32;
1601    #[link_name = "llvm.hexagon.S2.vrndpackwhs"]
1602    fn hexagon_S2_vrndpackwhs(_: i64) -> i32;
1603    #[link_name = "llvm.hexagon.S2.vsathb"]
1604    fn hexagon_S2_vsathb(_: i64) -> i32;
1605    #[link_name = "llvm.hexagon.S2.vsathb.nopack"]
1606    fn hexagon_S2_vsathb_nopack(_: i64) -> i64;
1607    #[link_name = "llvm.hexagon.S2.vsathub"]
1608    fn hexagon_S2_vsathub(_: i64) -> i32;
1609    #[link_name = "llvm.hexagon.S2.vsathub.nopack"]
1610    fn hexagon_S2_vsathub_nopack(_: i64) -> i64;
1611    #[link_name = "llvm.hexagon.S2.vsatwh"]
1612    fn hexagon_S2_vsatwh(_: i64) -> i32;
1613    #[link_name = "llvm.hexagon.S2.vsatwh.nopack"]
1614    fn hexagon_S2_vsatwh_nopack(_: i64) -> i64;
1615    #[link_name = "llvm.hexagon.S2.vsatwuh"]
1616    fn hexagon_S2_vsatwuh(_: i64) -> i32;
1617    #[link_name = "llvm.hexagon.S2.vsatwuh.nopack"]
1618    fn hexagon_S2_vsatwuh_nopack(_: i64) -> i64;
1619    #[link_name = "llvm.hexagon.S2.vsplatrb"]
1620    fn hexagon_S2_vsplatrb(_: i32) -> i32;
1621    #[link_name = "llvm.hexagon.S2.vsplatrh"]
1622    fn hexagon_S2_vsplatrh(_: i32) -> i64;
1623    #[link_name = "llvm.hexagon.S2.vspliceib"]
1624    fn hexagon_S2_vspliceib(_: i64, _: i64, _: i32) -> i64;
1625    #[link_name = "llvm.hexagon.S2.vsplicerb"]
1626    fn hexagon_S2_vsplicerb(_: i64, _: i64, _: i32) -> i64;
1627    #[link_name = "llvm.hexagon.S2.vsxtbh"]
1628    fn hexagon_S2_vsxtbh(_: i32) -> i64;
1629    #[link_name = "llvm.hexagon.S2.vsxthw"]
1630    fn hexagon_S2_vsxthw(_: i32) -> i64;
1631    #[link_name = "llvm.hexagon.S2.vtrunehb"]
1632    fn hexagon_S2_vtrunehb(_: i64) -> i32;
1633    #[link_name = "llvm.hexagon.S2.vtrunewh"]
1634    fn hexagon_S2_vtrunewh(_: i64, _: i64) -> i64;
1635    #[link_name = "llvm.hexagon.S2.vtrunohb"]
1636    fn hexagon_S2_vtrunohb(_: i64) -> i32;
1637    #[link_name = "llvm.hexagon.S2.vtrunowh"]
1638    fn hexagon_S2_vtrunowh(_: i64, _: i64) -> i64;
1639    #[link_name = "llvm.hexagon.S2.vzxtbh"]
1640    fn hexagon_S2_vzxtbh(_: i32) -> i64;
1641    #[link_name = "llvm.hexagon.S2.vzxthw"]
1642    fn hexagon_S2_vzxthw(_: i32) -> i64;
1643    #[link_name = "llvm.hexagon.S4.addaddi"]
1644    fn hexagon_S4_addaddi(_: i32, _: i32, _: i32) -> i32;
1645    #[link_name = "llvm.hexagon.S4.addi.asl.ri"]
1646    fn hexagon_S4_addi_asl_ri(_: i32, _: i32, _: i32) -> i32;
1647    #[link_name = "llvm.hexagon.S4.addi.lsr.ri"]
1648    fn hexagon_S4_addi_lsr_ri(_: i32, _: i32, _: i32) -> i32;
1649    #[link_name = "llvm.hexagon.S4.andi.asl.ri"]
1650    fn hexagon_S4_andi_asl_ri(_: i32, _: i32, _: i32) -> i32;
1651    #[link_name = "llvm.hexagon.S4.andi.lsr.ri"]
1652    fn hexagon_S4_andi_lsr_ri(_: i32, _: i32, _: i32) -> i32;
1653    #[link_name = "llvm.hexagon.S4.clbaddi"]
1654    fn hexagon_S4_clbaddi(_: i32, _: i32) -> i32;
1655    #[link_name = "llvm.hexagon.S4.clbpaddi"]
1656    fn hexagon_S4_clbpaddi(_: i64, _: i32) -> i32;
1657    #[link_name = "llvm.hexagon.S4.clbpnorm"]
1658    fn hexagon_S4_clbpnorm(_: i64) -> i32;
1659    #[link_name = "llvm.hexagon.S4.extract"]
1660    fn hexagon_S4_extract(_: i32, _: i32, _: i32) -> i32;
1661    #[link_name = "llvm.hexagon.S4.extract.rp"]
1662    fn hexagon_S4_extract_rp(_: i32, _: i64) -> i32;
1663    #[link_name = "llvm.hexagon.S4.extractp"]
1664    fn hexagon_S4_extractp(_: i64, _: i32, _: i32) -> i64;
1665    #[link_name = "llvm.hexagon.S4.extractp.rp"]
1666    fn hexagon_S4_extractp_rp(_: i64, _: i64) -> i64;
1667    #[link_name = "llvm.hexagon.S4.lsli"]
1668    fn hexagon_S4_lsli(_: i32, _: i32) -> i32;
1669    #[link_name = "llvm.hexagon.S4.ntstbit.i"]
1670    fn hexagon_S4_ntstbit_i(_: i32, _: i32) -> i32;
1671    #[link_name = "llvm.hexagon.S4.ntstbit.r"]
1672    fn hexagon_S4_ntstbit_r(_: i32, _: i32) -> i32;
1673    #[link_name = "llvm.hexagon.S4.or.andi"]
1674    fn hexagon_S4_or_andi(_: i32, _: i32, _: i32) -> i32;
1675    #[link_name = "llvm.hexagon.S4.or.andix"]
1676    fn hexagon_S4_or_andix(_: i32, _: i32, _: i32) -> i32;
1677    #[link_name = "llvm.hexagon.S4.or.ori"]
1678    fn hexagon_S4_or_ori(_: i32, _: i32, _: i32) -> i32;
1679    #[link_name = "llvm.hexagon.S4.ori.asl.ri"]
1680    fn hexagon_S4_ori_asl_ri(_: i32, _: i32, _: i32) -> i32;
1681    #[link_name = "llvm.hexagon.S4.ori.lsr.ri"]
1682    fn hexagon_S4_ori_lsr_ri(_: i32, _: i32, _: i32) -> i32;
1683    #[link_name = "llvm.hexagon.S4.parity"]
1684    fn hexagon_S4_parity(_: i32, _: i32) -> i32;
1685    #[link_name = "llvm.hexagon.S4.subaddi"]
1686    fn hexagon_S4_subaddi(_: i32, _: i32, _: i32) -> i32;
1687    #[link_name = "llvm.hexagon.S4.subi.asl.ri"]
1688    fn hexagon_S4_subi_asl_ri(_: i32, _: i32, _: i32) -> i32;
1689    #[link_name = "llvm.hexagon.S4.subi.lsr.ri"]
1690    fn hexagon_S4_subi_lsr_ri(_: i32, _: i32, _: i32) -> i32;
1691    #[link_name = "llvm.hexagon.S4.vrcrotate"]
1692    fn hexagon_S4_vrcrotate(_: i64, _: i32, _: i32) -> i64;
1693    #[link_name = "llvm.hexagon.S4.vrcrotate.acc"]
1694    fn hexagon_S4_vrcrotate_acc(_: i64, _: i64, _: i32, _: i32) -> i64;
1695    #[link_name = "llvm.hexagon.S4.vxaddsubh"]
1696    fn hexagon_S4_vxaddsubh(_: i64, _: i64) -> i64;
1697    #[link_name = "llvm.hexagon.S4.vxaddsubhr"]
1698    fn hexagon_S4_vxaddsubhr(_: i64, _: i64) -> i64;
1699    #[link_name = "llvm.hexagon.S4.vxaddsubw"]
1700    fn hexagon_S4_vxaddsubw(_: i64, _: i64) -> i64;
1701    #[link_name = "llvm.hexagon.S4.vxsubaddh"]
1702    fn hexagon_S4_vxsubaddh(_: i64, _: i64) -> i64;
1703    #[link_name = "llvm.hexagon.S4.vxsubaddhr"]
1704    fn hexagon_S4_vxsubaddhr(_: i64, _: i64) -> i64;
1705    #[link_name = "llvm.hexagon.S4.vxsubaddw"]
1706    fn hexagon_S4_vxsubaddw(_: i64, _: i64) -> i64;
1707    #[link_name = "llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax"]
1708    fn hexagon_S5_asrhub_rnd_sat_goodsyntax(_: i64, _: i32) -> i32;
1709    #[link_name = "llvm.hexagon.S5.asrhub.sat"]
1710    fn hexagon_S5_asrhub_sat(_: i64, _: i32) -> i32;
1711    #[link_name = "llvm.hexagon.S5.popcountp"]
1712    fn hexagon_S5_popcountp(_: i64) -> i32;
1713    #[link_name = "llvm.hexagon.S5.vasrhrnd.goodsyntax"]
1714    fn hexagon_S5_vasrhrnd_goodsyntax(_: i64, _: i32) -> i64;
1715    #[link_name = "llvm.hexagon.Y2.dccleana"]
1716    fn hexagon_Y2_dccleana(_: i32);
1717    #[link_name = "llvm.hexagon.Y2.dccleaninva"]
1718    fn hexagon_Y2_dccleaninva(_: i32);
1719    #[link_name = "llvm.hexagon.Y2.dcfetch"]
1720    fn hexagon_Y2_dcfetch(_: i32);
1721    #[link_name = "llvm.hexagon.Y2.dcinva"]
1722    fn hexagon_Y2_dcinva(_: i32);
1723    #[link_name = "llvm.hexagon.Y2.dczeroa"]
1724    fn hexagon_Y2_dczeroa(_: i32);
1725    #[link_name = "llvm.hexagon.Y4.l2fetch"]
1726    fn hexagon_Y4_l2fetch(_: i32, _: i32);
1727    #[link_name = "llvm.hexagon.Y5.l2fetch"]
1728    fn hexagon_Y5_l2fetch(_: i32, _: i64);
1729    #[link_name = "llvm.hexagon.S6.rol.i.p"]
1730    fn hexagon_S6_rol_i_p(_: i64, _: i32) -> i64;
1731    #[link_name = "llvm.hexagon.S6.rol.i.p.acc"]
1732    fn hexagon_S6_rol_i_p_acc(_: i64, _: i64, _: i32) -> i64;
1733    #[link_name = "llvm.hexagon.S6.rol.i.p.and"]
1734    fn hexagon_S6_rol_i_p_and(_: i64, _: i64, _: i32) -> i64;
1735    #[link_name = "llvm.hexagon.S6.rol.i.p.nac"]
1736    fn hexagon_S6_rol_i_p_nac(_: i64, _: i64, _: i32) -> i64;
1737    #[link_name = "llvm.hexagon.S6.rol.i.p.or"]
1738    fn hexagon_S6_rol_i_p_or(_: i64, _: i64, _: i32) -> i64;
1739    #[link_name = "llvm.hexagon.S6.rol.i.p.xacc"]
1740    fn hexagon_S6_rol_i_p_xacc(_: i64, _: i64, _: i32) -> i64;
1741    #[link_name = "llvm.hexagon.S6.rol.i.r"]
1742    fn hexagon_S6_rol_i_r(_: i32, _: i32) -> i32;
1743    #[link_name = "llvm.hexagon.S6.rol.i.r.acc"]
1744    fn hexagon_S6_rol_i_r_acc(_: i32, _: i32, _: i32) -> i32;
1745    #[link_name = "llvm.hexagon.S6.rol.i.r.and"]
1746    fn hexagon_S6_rol_i_r_and(_: i32, _: i32, _: i32) -> i32;
1747    #[link_name = "llvm.hexagon.S6.rol.i.r.nac"]
1748    fn hexagon_S6_rol_i_r_nac(_: i32, _: i32, _: i32) -> i32;
1749    #[link_name = "llvm.hexagon.S6.rol.i.r.or"]
1750    fn hexagon_S6_rol_i_r_or(_: i32, _: i32, _: i32) -> i32;
1751    #[link_name = "llvm.hexagon.S6.rol.i.r.xacc"]
1752    fn hexagon_S6_rol_i_r_xacc(_: i32, _: i32, _: i32) -> i32;
1753    #[link_name = "llvm.hexagon.M6.vabsdiffb"]
1754    fn hexagon_M6_vabsdiffb(_: i64, _: i64) -> i64;
1755    #[link_name = "llvm.hexagon.M6.vabsdiffub"]
1756    fn hexagon_M6_vabsdiffub(_: i64, _: i64) -> i64;
1757    #[link_name = "llvm.hexagon.S6.vsplatrbp"]
1758    fn hexagon_S6_vsplatrbp(_: i32) -> i64;
1759    #[link_name = "llvm.hexagon.S6.vtrunehb.ppp"]
1760    fn hexagon_S6_vtrunehb_ppp(_: i64, _: i64) -> i64;
1761    #[link_name = "llvm.hexagon.S6.vtrunohb.ppp"]
1762    fn hexagon_S6_vtrunohb_ppp(_: i64, _: i64) -> i64;
1763    #[link_name = "llvm.hexagon.A6.vcmpbeq.notany"]
1764    fn hexagon_A6_vcmpbeq_notany(_: i64, _: i64) -> i32;
1765    #[link_name = "llvm.hexagon.F2.dfadd"]
1766    fn hexagon_F2_dfadd(_: f64, _: f64) -> f64;
1767    #[link_name = "llvm.hexagon.F2.dfsub"]
1768    fn hexagon_F2_dfsub(_: f64, _: f64) -> f64;
1769    #[link_name = "llvm.hexagon.M2.mnaci"]
1770    fn hexagon_M2_mnaci(_: i32, _: i32, _: i32) -> i32;
1771    #[link_name = "llvm.hexagon.S2.mask"]
1772    fn hexagon_S2_mask(_: i32, _: i32) -> i32;
1773    #[link_name = "llvm.hexagon.A7.clip"]
1774    fn hexagon_A7_clip(_: i32, _: i32) -> i32;
1775    #[link_name = "llvm.hexagon.A7.croundd.ri"]
1776    fn hexagon_A7_croundd_ri(_: i64, _: i32) -> i64;
1777    #[link_name = "llvm.hexagon.A7.croundd.rr"]
1778    fn hexagon_A7_croundd_rr(_: i64, _: i32) -> i64;
1779    #[link_name = "llvm.hexagon.A7.vclip"]
1780    fn hexagon_A7_vclip(_: i64, _: i32) -> i64;
1781    #[link_name = "llvm.hexagon.F2.dfmax"]
1782    fn hexagon_F2_dfmax(_: f64, _: f64) -> f64;
1783    #[link_name = "llvm.hexagon.F2.dfmin"]
1784    fn hexagon_F2_dfmin(_: f64, _: f64) -> f64;
1785    #[link_name = "llvm.hexagon.F2.dfmpyfix"]
1786    fn hexagon_F2_dfmpyfix(_: f64, _: f64) -> f64;
1787    #[link_name = "llvm.hexagon.F2.dfmpyhh"]
1788    fn hexagon_F2_dfmpyhh(_: f64, _: f64, _: f64) -> f64;
1789    #[link_name = "llvm.hexagon.F2.dfmpylh"]
1790    fn hexagon_F2_dfmpylh(_: f64, _: f64, _: f64) -> f64;
1791    #[link_name = "llvm.hexagon.F2.dfmpyll"]
1792    fn hexagon_F2_dfmpyll(_: f64, _: f64) -> f64;
1793    #[link_name = "llvm.hexagon.M7.dcmpyiw"]
1794    fn hexagon_M7_dcmpyiw(_: i64, _: i64) -> i64;
1795    #[link_name = "llvm.hexagon.M7.dcmpyiw.acc"]
1796    fn hexagon_M7_dcmpyiw_acc(_: i64, _: i64, _: i64) -> i64;
1797    #[link_name = "llvm.hexagon.M7.dcmpyiwc"]
1798    fn hexagon_M7_dcmpyiwc(_: i64, _: i64) -> i64;
1799    #[link_name = "llvm.hexagon.M7.dcmpyiwc.acc"]
1800    fn hexagon_M7_dcmpyiwc_acc(_: i64, _: i64, _: i64) -> i64;
1801    #[link_name = "llvm.hexagon.M7.dcmpyrw"]
1802    fn hexagon_M7_dcmpyrw(_: i64, _: i64) -> i64;
1803    #[link_name = "llvm.hexagon.M7.dcmpyrw.acc"]
1804    fn hexagon_M7_dcmpyrw_acc(_: i64, _: i64, _: i64) -> i64;
1805    #[link_name = "llvm.hexagon.M7.dcmpyrwc"]
1806    fn hexagon_M7_dcmpyrwc(_: i64, _: i64) -> i64;
1807    #[link_name = "llvm.hexagon.M7.dcmpyrwc.acc"]
1808    fn hexagon_M7_dcmpyrwc_acc(_: i64, _: i64, _: i64) -> i64;
1809    #[link_name = "llvm.hexagon.M7.vdmpy"]
1810    fn hexagon_M7_vdmpy(_: i64, _: i64) -> i64;
1811    #[link_name = "llvm.hexagon.M7.vdmpy.acc"]
1812    fn hexagon_M7_vdmpy_acc(_: i64, _: i64, _: i64) -> i64;
1813    #[link_name = "llvm.hexagon.M7.wcmpyiw"]
1814    fn hexagon_M7_wcmpyiw(_: i64, _: i64) -> i32;
1815    #[link_name = "llvm.hexagon.M7.wcmpyiw.rnd"]
1816    fn hexagon_M7_wcmpyiw_rnd(_: i64, _: i64) -> i32;
1817    #[link_name = "llvm.hexagon.M7.wcmpyiwc"]
1818    fn hexagon_M7_wcmpyiwc(_: i64, _: i64) -> i32;
1819    #[link_name = "llvm.hexagon.M7.wcmpyiwc.rnd"]
1820    fn hexagon_M7_wcmpyiwc_rnd(_: i64, _: i64) -> i32;
1821    #[link_name = "llvm.hexagon.M7.wcmpyrw"]
1822    fn hexagon_M7_wcmpyrw(_: i64, _: i64) -> i32;
1823    #[link_name = "llvm.hexagon.M7.wcmpyrw.rnd"]
1824    fn hexagon_M7_wcmpyrw_rnd(_: i64, _: i64) -> i32;
1825    #[link_name = "llvm.hexagon.M7.wcmpyrwc"]
1826    fn hexagon_M7_wcmpyrwc(_: i64, _: i64) -> i32;
1827    #[link_name = "llvm.hexagon.M7.wcmpyrwc.rnd"]
1828    fn hexagon_M7_wcmpyrwc_rnd(_: i64, _: i64) -> i32;
1829    #[link_name = "llvm.hexagon.Y6.dmlink"]
1830    fn hexagon_Y6_dmlink(_: i32, _: i32);
1831    #[link_name = "llvm.hexagon.Y6.dmpause"]
1832    fn hexagon_Y6_dmpause() -> i32;
1833    #[link_name = "llvm.hexagon.Y6.dmpoll"]
1834    fn hexagon_Y6_dmpoll() -> i32;
1835    #[link_name = "llvm.hexagon.Y6.dmresume"]
1836    fn hexagon_Y6_dmresume(_: i32);
1837    #[link_name = "llvm.hexagon.Y6.dmstart"]
1838    fn hexagon_Y6_dmstart(_: i32);
1839    #[link_name = "llvm.hexagon.Y6.dmwait"]
1840    fn hexagon_Y6_dmwait() -> i32;
1841}
1842
1843/// `Rd32=abs(Rs32)`
1844///
1845/// Instruction Type: S_2op
1846/// Execution Slots: SLOT23
1847#[inline(always)]
1848#[cfg_attr(test, assert_instr(abs))]
1849#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1850pub unsafe fn Q6_R_abs_R(rs: i32) -> i32 {
1851    hexagon_A2_abs(rs)
1852}
1853
1854/// `Rdd32=abs(Rss32)`
1855///
1856/// Instruction Type: S_2op
1857/// Execution Slots: SLOT23
1858#[inline(always)]
1859#[cfg_attr(test, assert_instr(abs))]
1860#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1861pub unsafe fn Q6_P_abs_P(rss: i64) -> i64 {
1862    hexagon_A2_absp(rss)
1863}
1864
1865/// `Rd32=abs(Rs32):sat`
1866///
1867/// Instruction Type: S_2op
1868/// Execution Slots: SLOT23
1869#[inline(always)]
1870#[cfg_attr(test, assert_instr(abs))]
1871#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1872pub unsafe fn Q6_R_abs_R_sat(rs: i32) -> i32 {
1873    hexagon_A2_abssat(rs)
1874}
1875
1876/// `Rd32=add(Rs32,Rt32)`
1877///
1878/// Instruction Type: ALU32_3op
1879/// Execution Slots: SLOT0123
1880#[inline(always)]
1881#[cfg_attr(test, assert_instr(add))]
1882#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1883pub unsafe fn Q6_R_add_RR(rs: i32, rt: i32) -> i32 {
1884    hexagon_A2_add(rs, rt)
1885}
1886
1887/// `Rd32=add(Rt32.h,Rs32.h):<<16`
1888///
1889/// Instruction Type: ALU64
1890/// Execution Slots: SLOT23
1891#[inline(always)]
1892#[cfg_attr(test, assert_instr(add))]
1893#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1894pub unsafe fn Q6_R_add_RhRh_s16(rt: i32, rs: i32) -> i32 {
1895    hexagon_A2_addh_h16_hh(rt, rs)
1896}
1897
1898/// `Rd32=add(Rt32.h,Rs32.l):<<16`
1899///
1900/// Instruction Type: ALU64
1901/// Execution Slots: SLOT23
1902#[inline(always)]
1903#[cfg_attr(test, assert_instr(add))]
1904#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1905pub unsafe fn Q6_R_add_RhRl_s16(rt: i32, rs: i32) -> i32 {
1906    hexagon_A2_addh_h16_hl(rt, rs)
1907}
1908
1909/// `Rd32=add(Rt32.l,Rs32.h):<<16`
1910///
1911/// Instruction Type: ALU64
1912/// Execution Slots: SLOT23
1913#[inline(always)]
1914#[cfg_attr(test, assert_instr(add))]
1915#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1916pub unsafe fn Q6_R_add_RlRh_s16(rt: i32, rs: i32) -> i32 {
1917    hexagon_A2_addh_h16_lh(rt, rs)
1918}
1919
1920/// `Rd32=add(Rt32.l,Rs32.l):<<16`
1921///
1922/// Instruction Type: ALU64
1923/// Execution Slots: SLOT23
1924#[inline(always)]
1925#[cfg_attr(test, assert_instr(add))]
1926#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1927pub unsafe fn Q6_R_add_RlRl_s16(rt: i32, rs: i32) -> i32 {
1928    hexagon_A2_addh_h16_ll(rt, rs)
1929}
1930
1931/// `Rd32=add(Rt32.h,Rs32.h):sat:<<16`
1932///
1933/// Instruction Type: ALU64
1934/// Execution Slots: SLOT23
1935#[inline(always)]
1936#[cfg_attr(test, assert_instr(add))]
1937#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1938pub unsafe fn Q6_R_add_RhRh_sat_s16(rt: i32, rs: i32) -> i32 {
1939    hexagon_A2_addh_h16_sat_hh(rt, rs)
1940}
1941
1942/// `Rd32=add(Rt32.h,Rs32.l):sat:<<16`
1943///
1944/// Instruction Type: ALU64
1945/// Execution Slots: SLOT23
1946#[inline(always)]
1947#[cfg_attr(test, assert_instr(add))]
1948#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1949pub unsafe fn Q6_R_add_RhRl_sat_s16(rt: i32, rs: i32) -> i32 {
1950    hexagon_A2_addh_h16_sat_hl(rt, rs)
1951}
1952
1953/// `Rd32=add(Rt32.l,Rs32.h):sat:<<16`
1954///
1955/// Instruction Type: ALU64
1956/// Execution Slots: SLOT23
1957#[inline(always)]
1958#[cfg_attr(test, assert_instr(add))]
1959#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1960pub unsafe fn Q6_R_add_RlRh_sat_s16(rt: i32, rs: i32) -> i32 {
1961    hexagon_A2_addh_h16_sat_lh(rt, rs)
1962}
1963
1964/// `Rd32=add(Rt32.l,Rs32.l):sat:<<16`
1965///
1966/// Instruction Type: ALU64
1967/// Execution Slots: SLOT23
1968#[inline(always)]
1969#[cfg_attr(test, assert_instr(add))]
1970#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1971pub unsafe fn Q6_R_add_RlRl_sat_s16(rt: i32, rs: i32) -> i32 {
1972    hexagon_A2_addh_h16_sat_ll(rt, rs)
1973}
1974
1975/// `Rd32=add(Rt32.l,Rs32.h)`
1976///
1977/// Instruction Type: ALU64
1978/// Execution Slots: SLOT23
1979#[inline(always)]
1980#[cfg_attr(test, assert_instr(add))]
1981#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1982pub unsafe fn Q6_R_add_RlRh(rt: i32, rs: i32) -> i32 {
1983    hexagon_A2_addh_l16_hl(rt, rs)
1984}
1985
1986/// `Rd32=add(Rt32.l,Rs32.l)`
1987///
1988/// Instruction Type: ALU64
1989/// Execution Slots: SLOT23
1990#[inline(always)]
1991#[cfg_attr(test, assert_instr(add))]
1992#[unstable(feature = "stdarch_hexagon", issue = "151523")]
1993pub unsafe fn Q6_R_add_RlRl(rt: i32, rs: i32) -> i32 {
1994    hexagon_A2_addh_l16_ll(rt, rs)
1995}
1996
1997/// `Rd32=add(Rt32.l,Rs32.h):sat`
1998///
1999/// Instruction Type: ALU64
2000/// Execution Slots: SLOT23
2001#[inline(always)]
2002#[cfg_attr(test, assert_instr(add))]
2003#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2004pub unsafe fn Q6_R_add_RlRh_sat(rt: i32, rs: i32) -> i32 {
2005    hexagon_A2_addh_l16_sat_hl(rt, rs)
2006}
2007
2008/// `Rd32=add(Rt32.l,Rs32.l):sat`
2009///
2010/// Instruction Type: ALU64
2011/// Execution Slots: SLOT23
2012#[inline(always)]
2013#[cfg_attr(test, assert_instr(add))]
2014#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2015pub unsafe fn Q6_R_add_RlRl_sat(rt: i32, rs: i32) -> i32 {
2016    hexagon_A2_addh_l16_sat_ll(rt, rs)
2017}
2018
2019/// `Rd32=add(Rs32,#s16)`
2020///
2021/// Instruction Type: ALU32_ADDI
2022/// Execution Slots: SLOT0123
2023#[inline(always)]
2024#[rustc_legacy_const_generics(1)]
2025#[cfg_attr(test, assert_instr(add, IS16 = 0))]
2026#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2027pub unsafe fn Q6_R_add_RI<const IS16: i32>(rs: i32) -> i32 {
2028    static_assert_simm_bits!(IS16, 16);
2029    hexagon_A2_addi(rs, IS16)
2030}
2031
2032/// `Rdd32=add(Rss32,Rtt32)`
2033///
2034/// Instruction Type: ALU64
2035/// Execution Slots: SLOT23
2036#[inline(always)]
2037#[cfg_attr(test, assert_instr(add))]
2038#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2039pub unsafe fn Q6_P_add_PP(rss: i64, rtt: i64) -> i64 {
2040    hexagon_A2_addp(rss, rtt)
2041}
2042
2043/// `Rdd32=add(Rss32,Rtt32):sat`
2044///
2045/// Instruction Type: ALU64
2046/// Execution Slots: SLOT23
2047#[inline(always)]
2048#[cfg_attr(test, assert_instr(add))]
2049#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2050pub unsafe fn Q6_P_add_PP_sat(rss: i64, rtt: i64) -> i64 {
2051    hexagon_A2_addpsat(rss, rtt)
2052}
2053
2054/// `Rd32=add(Rs32,Rt32):sat`
2055///
2056/// Instruction Type: ALU32_3op
2057/// Execution Slots: SLOT0123
2058#[inline(always)]
2059#[cfg_attr(test, assert_instr(add))]
2060#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2061pub unsafe fn Q6_R_add_RR_sat(rs: i32, rt: i32) -> i32 {
2062    hexagon_A2_addsat(rs, rt)
2063}
2064
2065/// `Rdd32=add(Rs32,Rtt32)`
2066///
2067/// Instruction Type: ALU64
2068/// Execution Slots: SLOT0123
2069#[inline(always)]
2070#[cfg_attr(test, assert_instr(add))]
2071#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2072pub unsafe fn Q6_P_add_RP(rs: i32, rtt: i64) -> i64 {
2073    hexagon_A2_addsp(rs, rtt)
2074}
2075
2076/// `Rd32=and(Rs32,Rt32)`
2077///
2078/// Instruction Type: ALU32_3op
2079/// Execution Slots: SLOT0123
2080#[inline(always)]
2081#[cfg_attr(test, assert_instr(and))]
2082#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2083pub unsafe fn Q6_R_and_RR(rs: i32, rt: i32) -> i32 {
2084    hexagon_A2_and(rs, rt)
2085}
2086
2087/// `Rd32=and(Rs32,#s10)`
2088///
2089/// Instruction Type: ALU32_2op
2090/// Execution Slots: SLOT0123
2091#[inline(always)]
2092#[rustc_legacy_const_generics(1)]
2093#[cfg_attr(test, assert_instr(and, IS10 = 0))]
2094#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2095pub unsafe fn Q6_R_and_RI<const IS10: i32>(rs: i32) -> i32 {
2096    static_assert_simm_bits!(IS10, 10);
2097    hexagon_A2_andir(rs, IS10)
2098}
2099
2100/// `Rdd32=and(Rss32,Rtt32)`
2101///
2102/// Instruction Type: ALU64
2103/// Execution Slots: SLOT23
2104#[inline(always)]
2105#[cfg_attr(test, assert_instr(and))]
2106#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2107pub unsafe fn Q6_P_and_PP(rss: i64, rtt: i64) -> i64 {
2108    hexagon_A2_andp(rss, rtt)
2109}
2110
2111/// `Rd32=aslh(Rs32)`
2112///
2113/// Instruction Type: ALU32_2op
2114/// Execution Slots: SLOT0123
2115#[inline(always)]
2116#[cfg_attr(test, assert_instr(aslh))]
2117#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2118pub unsafe fn Q6_R_aslh_R(rs: i32) -> i32 {
2119    hexagon_A2_aslh(rs)
2120}
2121
2122/// `Rd32=asrh(Rs32)`
2123///
2124/// Instruction Type: ALU32_2op
2125/// Execution Slots: SLOT0123
2126#[inline(always)]
2127#[cfg_attr(test, assert_instr(asrh))]
2128#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2129pub unsafe fn Q6_R_asrh_R(rs: i32) -> i32 {
2130    hexagon_A2_asrh(rs)
2131}
2132
2133/// `Rd32=combine(Rt32.h,Rs32.h)`
2134///
2135/// Instruction Type: ALU32_3op
2136/// Execution Slots: SLOT0123
2137#[inline(always)]
2138#[cfg_attr(test, assert_instr(combine))]
2139#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2140pub unsafe fn Q6_R_combine_RhRh(rt: i32, rs: i32) -> i32 {
2141    hexagon_A2_combine_hh(rt, rs)
2142}
2143
2144/// `Rd32=combine(Rt32.h,Rs32.l)`
2145///
2146/// Instruction Type: ALU32_3op
2147/// Execution Slots: SLOT0123
2148#[inline(always)]
2149#[cfg_attr(test, assert_instr(combine))]
2150#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2151pub unsafe fn Q6_R_combine_RhRl(rt: i32, rs: i32) -> i32 {
2152    hexagon_A2_combine_hl(rt, rs)
2153}
2154
2155/// `Rd32=combine(Rt32.l,Rs32.h)`
2156///
2157/// Instruction Type: ALU32_3op
2158/// Execution Slots: SLOT0123
2159#[inline(always)]
2160#[cfg_attr(test, assert_instr(combine))]
2161#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2162pub unsafe fn Q6_R_combine_RlRh(rt: i32, rs: i32) -> i32 {
2163    hexagon_A2_combine_lh(rt, rs)
2164}
2165
2166/// `Rd32=combine(Rt32.l,Rs32.l)`
2167///
2168/// Instruction Type: ALU32_3op
2169/// Execution Slots: SLOT0123
2170#[inline(always)]
2171#[cfg_attr(test, assert_instr(combine))]
2172#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2173pub unsafe fn Q6_R_combine_RlRl(rt: i32, rs: i32) -> i32 {
2174    hexagon_A2_combine_ll(rt, rs)
2175}
2176
2177/// `Rdd32=combine(#s8,#S8)`
2178///
2179/// Instruction Type: ALU32_2op
2180/// Execution Slots: SLOT0123
2181#[inline(always)]
2182#[rustc_legacy_const_generics(0, 1)]
2183#[cfg_attr(test, assert_instr(combine, IS8 = 0, IS8_2 = 0))]
2184#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2185pub unsafe fn Q6_P_combine_II<const IS8: i32, const IS8_2: i32>() -> i64 {
2186    static_assert_simm_bits!(IS8, 8);
2187    static_assert_simm_bits!(IS8_2, 8);
2188    hexagon_A2_combineii(IS8, IS8_2)
2189}
2190
2191/// `Rdd32=combine(Rs32,Rt32)`
2192///
2193/// Instruction Type: ALU32_3op
2194/// Execution Slots: SLOT0123
2195#[inline(always)]
2196#[cfg_attr(test, assert_instr(combine))]
2197#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2198pub unsafe fn Q6_P_combine_RR(rs: i32, rt: i32) -> i64 {
2199    hexagon_A2_combinew(rs, rt)
2200}
2201
2202/// `Rd32=max(Rs32,Rt32)`
2203///
2204/// Instruction Type: ALU64
2205/// Execution Slots: SLOT23
2206#[inline(always)]
2207#[cfg_attr(test, assert_instr(max))]
2208#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2209pub unsafe fn Q6_R_max_RR(rs: i32, rt: i32) -> i32 {
2210    hexagon_A2_max(rs, rt)
2211}
2212
2213/// `Rdd32=max(Rss32,Rtt32)`
2214///
2215/// Instruction Type: ALU64
2216/// Execution Slots: SLOT23
2217#[inline(always)]
2218#[cfg_attr(test, assert_instr(max))]
2219#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2220pub unsafe fn Q6_P_max_PP(rss: i64, rtt: i64) -> i64 {
2221    hexagon_A2_maxp(rss, rtt)
2222}
2223
2224/// `Rd32=maxu(Rs32,Rt32)`
2225///
2226/// Instruction Type: ALU64
2227/// Execution Slots: SLOT23
2228#[inline(always)]
2229#[cfg_attr(test, assert_instr(maxu))]
2230#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2231pub unsafe fn Q6_R_maxu_RR(rs: i32, rt: i32) -> i32 {
2232    hexagon_A2_maxu(rs, rt)
2233}
2234
2235/// `Rdd32=maxu(Rss32,Rtt32)`
2236///
2237/// Instruction Type: ALU64
2238/// Execution Slots: SLOT23
2239#[inline(always)]
2240#[cfg_attr(test, assert_instr(maxu))]
2241#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2242pub unsafe fn Q6_P_maxu_PP(rss: i64, rtt: i64) -> i64 {
2243    hexagon_A2_maxup(rss, rtt)
2244}
2245
2246/// `Rd32=min(Rt32,Rs32)`
2247///
2248/// Instruction Type: ALU64
2249/// Execution Slots: SLOT23
2250#[inline(always)]
2251#[cfg_attr(test, assert_instr(min))]
2252#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2253pub unsafe fn Q6_R_min_RR(rt: i32, rs: i32) -> i32 {
2254    hexagon_A2_min(rt, rs)
2255}
2256
2257/// `Rdd32=min(Rtt32,Rss32)`
2258///
2259/// Instruction Type: ALU64
2260/// Execution Slots: SLOT23
2261#[inline(always)]
2262#[cfg_attr(test, assert_instr(min))]
2263#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2264pub unsafe fn Q6_P_min_PP(rtt: i64, rss: i64) -> i64 {
2265    hexagon_A2_minp(rtt, rss)
2266}
2267
2268/// `Rd32=minu(Rt32,Rs32)`
2269///
2270/// Instruction Type: ALU64
2271/// Execution Slots: SLOT23
2272#[inline(always)]
2273#[cfg_attr(test, assert_instr(minu))]
2274#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2275pub unsafe fn Q6_R_minu_RR(rt: i32, rs: i32) -> i32 {
2276    hexagon_A2_minu(rt, rs)
2277}
2278
2279/// `Rdd32=minu(Rtt32,Rss32)`
2280///
2281/// Instruction Type: ALU64
2282/// Execution Slots: SLOT23
2283#[inline(always)]
2284#[cfg_attr(test, assert_instr(minu))]
2285#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2286pub unsafe fn Q6_P_minu_PP(rtt: i64, rss: i64) -> i64 {
2287    hexagon_A2_minup(rtt, rss)
2288}
2289
2290/// `Rd32=neg(Rs32)`
2291///
2292/// Instruction Type: ALU32_2op
2293/// Execution Slots: SLOT0123
2294#[inline(always)]
2295#[cfg_attr(test, assert_instr(neg))]
2296#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2297pub unsafe fn Q6_R_neg_R(rs: i32) -> i32 {
2298    hexagon_A2_neg(rs)
2299}
2300
2301/// `Rdd32=neg(Rss32)`
2302///
2303/// Instruction Type: S_2op
2304/// Execution Slots: SLOT23
2305#[inline(always)]
2306#[cfg_attr(test, assert_instr(neg))]
2307#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2308pub unsafe fn Q6_P_neg_P(rss: i64) -> i64 {
2309    hexagon_A2_negp(rss)
2310}
2311
2312/// `Rd32=neg(Rs32):sat`
2313///
2314/// Instruction Type: S_2op
2315/// Execution Slots: SLOT23
2316#[inline(always)]
2317#[cfg_attr(test, assert_instr(neg))]
2318#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2319pub unsafe fn Q6_R_neg_R_sat(rs: i32) -> i32 {
2320    hexagon_A2_negsat(rs)
2321}
2322
2323/// `Rd32=not(Rs32)`
2324///
2325/// Instruction Type: ALU32_2op
2326/// Execution Slots: SLOT0123
2327#[inline(always)]
2328#[cfg_attr(test, assert_instr(not))]
2329#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2330pub unsafe fn Q6_R_not_R(rs: i32) -> i32 {
2331    hexagon_A2_not(rs)
2332}
2333
2334/// `Rdd32=not(Rss32)`
2335///
2336/// Instruction Type: S_2op
2337/// Execution Slots: SLOT23
2338#[inline(always)]
2339#[cfg_attr(test, assert_instr(not))]
2340#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2341pub unsafe fn Q6_P_not_P(rss: i64) -> i64 {
2342    hexagon_A2_notp(rss)
2343}
2344
2345/// `Rd32=or(Rs32,Rt32)`
2346///
2347/// Instruction Type: ALU32_3op
2348/// Execution Slots: SLOT0123
2349#[inline(always)]
2350#[cfg_attr(test, assert_instr(or))]
2351#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2352pub unsafe fn Q6_R_or_RR(rs: i32, rt: i32) -> i32 {
2353    hexagon_A2_or(rs, rt)
2354}
2355
2356/// `Rd32=or(Rs32,#s10)`
2357///
2358/// Instruction Type: ALU32_2op
2359/// Execution Slots: SLOT0123
2360#[inline(always)]
2361#[rustc_legacy_const_generics(1)]
2362#[cfg_attr(test, assert_instr(or, IS10 = 0))]
2363#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2364pub unsafe fn Q6_R_or_RI<const IS10: i32>(rs: i32) -> i32 {
2365    static_assert_simm_bits!(IS10, 10);
2366    hexagon_A2_orir(rs, IS10)
2367}
2368
2369/// `Rdd32=or(Rss32,Rtt32)`
2370///
2371/// Instruction Type: ALU64
2372/// Execution Slots: SLOT23
2373#[inline(always)]
2374#[cfg_attr(test, assert_instr(or))]
2375#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2376pub unsafe fn Q6_P_or_PP(rss: i64, rtt: i64) -> i64 {
2377    hexagon_A2_orp(rss, rtt)
2378}
2379
2380/// `Rd32=round(Rss32):sat`
2381///
2382/// Instruction Type: S_2op
2383/// Execution Slots: SLOT23
2384#[inline(always)]
2385#[cfg_attr(test, assert_instr(round))]
2386#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2387pub unsafe fn Q6_R_round_P_sat(rss: i64) -> i32 {
2388    hexagon_A2_roundsat(rss)
2389}
2390
2391/// `Rd32=sat(Rss32)`
2392///
2393/// Instruction Type: S_2op
2394/// Execution Slots: SLOT23
2395#[inline(always)]
2396#[cfg_attr(test, assert_instr(sat))]
2397#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2398pub unsafe fn Q6_R_sat_P(rss: i64) -> i32 {
2399    hexagon_A2_sat(rss)
2400}
2401
2402/// `Rd32=satb(Rs32)`
2403///
2404/// Instruction Type: S_2op
2405/// Execution Slots: SLOT23
2406#[inline(always)]
2407#[cfg_attr(test, assert_instr(satb))]
2408#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2409pub unsafe fn Q6_R_satb_R(rs: i32) -> i32 {
2410    hexagon_A2_satb(rs)
2411}
2412
2413/// `Rd32=sath(Rs32)`
2414///
2415/// Instruction Type: S_2op
2416/// Execution Slots: SLOT23
2417#[inline(always)]
2418#[cfg_attr(test, assert_instr(sath))]
2419#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2420pub unsafe fn Q6_R_sath_R(rs: i32) -> i32 {
2421    hexagon_A2_sath(rs)
2422}
2423
2424/// `Rd32=satub(Rs32)`
2425///
2426/// Instruction Type: S_2op
2427/// Execution Slots: SLOT23
2428#[inline(always)]
2429#[cfg_attr(test, assert_instr(satub))]
2430#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2431pub unsafe fn Q6_R_satub_R(rs: i32) -> i32 {
2432    hexagon_A2_satub(rs)
2433}
2434
2435/// `Rd32=satuh(Rs32)`
2436///
2437/// Instruction Type: S_2op
2438/// Execution Slots: SLOT23
2439#[inline(always)]
2440#[cfg_attr(test, assert_instr(satuh))]
2441#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2442pub unsafe fn Q6_R_satuh_R(rs: i32) -> i32 {
2443    hexagon_A2_satuh(rs)
2444}
2445
2446/// `Rd32=sub(Rt32,Rs32)`
2447///
2448/// Instruction Type: ALU32_3op
2449/// Execution Slots: SLOT0123
2450#[inline(always)]
2451#[cfg_attr(test, assert_instr(sub))]
2452#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2453pub unsafe fn Q6_R_sub_RR(rt: i32, rs: i32) -> i32 {
2454    hexagon_A2_sub(rt, rs)
2455}
2456
2457/// `Rd32=sub(Rt32.h,Rs32.h):<<16`
2458///
2459/// Instruction Type: ALU64
2460/// Execution Slots: SLOT23
2461#[inline(always)]
2462#[cfg_attr(test, assert_instr(sub))]
2463#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2464pub unsafe fn Q6_R_sub_RhRh_s16(rt: i32, rs: i32) -> i32 {
2465    hexagon_A2_subh_h16_hh(rt, rs)
2466}
2467
2468/// `Rd32=sub(Rt32.h,Rs32.l):<<16`
2469///
2470/// Instruction Type: ALU64
2471/// Execution Slots: SLOT23
2472#[inline(always)]
2473#[cfg_attr(test, assert_instr(sub))]
2474#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2475pub unsafe fn Q6_R_sub_RhRl_s16(rt: i32, rs: i32) -> i32 {
2476    hexagon_A2_subh_h16_hl(rt, rs)
2477}
2478
2479/// `Rd32=sub(Rt32.l,Rs32.h):<<16`
2480///
2481/// Instruction Type: ALU64
2482/// Execution Slots: SLOT23
2483#[inline(always)]
2484#[cfg_attr(test, assert_instr(sub))]
2485#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2486pub unsafe fn Q6_R_sub_RlRh_s16(rt: i32, rs: i32) -> i32 {
2487    hexagon_A2_subh_h16_lh(rt, rs)
2488}
2489
2490/// `Rd32=sub(Rt32.l,Rs32.l):<<16`
2491///
2492/// Instruction Type: ALU64
2493/// Execution Slots: SLOT23
2494#[inline(always)]
2495#[cfg_attr(test, assert_instr(sub))]
2496#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2497pub unsafe fn Q6_R_sub_RlRl_s16(rt: i32, rs: i32) -> i32 {
2498    hexagon_A2_subh_h16_ll(rt, rs)
2499}
2500
2501/// `Rd32=sub(Rt32.h,Rs32.h):sat:<<16`
2502///
2503/// Instruction Type: ALU64
2504/// Execution Slots: SLOT23
2505#[inline(always)]
2506#[cfg_attr(test, assert_instr(sub))]
2507#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2508pub unsafe fn Q6_R_sub_RhRh_sat_s16(rt: i32, rs: i32) -> i32 {
2509    hexagon_A2_subh_h16_sat_hh(rt, rs)
2510}
2511
2512/// `Rd32=sub(Rt32.h,Rs32.l):sat:<<16`
2513///
2514/// Instruction Type: ALU64
2515/// Execution Slots: SLOT23
2516#[inline(always)]
2517#[cfg_attr(test, assert_instr(sub))]
2518#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2519pub unsafe fn Q6_R_sub_RhRl_sat_s16(rt: i32, rs: i32) -> i32 {
2520    hexagon_A2_subh_h16_sat_hl(rt, rs)
2521}
2522
2523/// `Rd32=sub(Rt32.l,Rs32.h):sat:<<16`
2524///
2525/// Instruction Type: ALU64
2526/// Execution Slots: SLOT23
2527#[inline(always)]
2528#[cfg_attr(test, assert_instr(sub))]
2529#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2530pub unsafe fn Q6_R_sub_RlRh_sat_s16(rt: i32, rs: i32) -> i32 {
2531    hexagon_A2_subh_h16_sat_lh(rt, rs)
2532}
2533
2534/// `Rd32=sub(Rt32.l,Rs32.l):sat:<<16`
2535///
2536/// Instruction Type: ALU64
2537/// Execution Slots: SLOT23
2538#[inline(always)]
2539#[cfg_attr(test, assert_instr(sub))]
2540#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2541pub unsafe fn Q6_R_sub_RlRl_sat_s16(rt: i32, rs: i32) -> i32 {
2542    hexagon_A2_subh_h16_sat_ll(rt, rs)
2543}
2544
2545/// `Rd32=sub(Rt32.l,Rs32.h)`
2546///
2547/// Instruction Type: ALU64
2548/// Execution Slots: SLOT23
2549#[inline(always)]
2550#[cfg_attr(test, assert_instr(sub))]
2551#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2552pub unsafe fn Q6_R_sub_RlRh(rt: i32, rs: i32) -> i32 {
2553    hexagon_A2_subh_l16_hl(rt, rs)
2554}
2555
2556/// `Rd32=sub(Rt32.l,Rs32.l)`
2557///
2558/// Instruction Type: ALU64
2559/// Execution Slots: SLOT23
2560#[inline(always)]
2561#[cfg_attr(test, assert_instr(sub))]
2562#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2563pub unsafe fn Q6_R_sub_RlRl(rt: i32, rs: i32) -> i32 {
2564    hexagon_A2_subh_l16_ll(rt, rs)
2565}
2566
2567/// `Rd32=sub(Rt32.l,Rs32.h):sat`
2568///
2569/// Instruction Type: ALU64
2570/// Execution Slots: SLOT23
2571#[inline(always)]
2572#[cfg_attr(test, assert_instr(sub))]
2573#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2574pub unsafe fn Q6_R_sub_RlRh_sat(rt: i32, rs: i32) -> i32 {
2575    hexagon_A2_subh_l16_sat_hl(rt, rs)
2576}
2577
2578/// `Rd32=sub(Rt32.l,Rs32.l):sat`
2579///
2580/// Instruction Type: ALU64
2581/// Execution Slots: SLOT23
2582#[inline(always)]
2583#[cfg_attr(test, assert_instr(sub))]
2584#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2585pub unsafe fn Q6_R_sub_RlRl_sat(rt: i32, rs: i32) -> i32 {
2586    hexagon_A2_subh_l16_sat_ll(rt, rs)
2587}
2588
2589/// `Rdd32=sub(Rtt32,Rss32)`
2590///
2591/// Instruction Type: ALU64
2592/// Execution Slots: SLOT23
2593#[inline(always)]
2594#[cfg_attr(test, assert_instr(sub))]
2595#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2596pub unsafe fn Q6_P_sub_PP(rtt: i64, rss: i64) -> i64 {
2597    hexagon_A2_subp(rtt, rss)
2598}
2599
2600/// `Rd32=sub(#s10,Rs32)`
2601///
2602/// Instruction Type: ALU32_2op
2603/// Execution Slots: SLOT0123
2604#[inline(always)]
2605#[rustc_legacy_const_generics(0)]
2606#[cfg_attr(test, assert_instr(sub, IS10 = 0))]
2607#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2608pub unsafe fn Q6_R_sub_IR<const IS10: i32>(rs: i32) -> i32 {
2609    static_assert_simm_bits!(IS10, 10);
2610    hexagon_A2_subri(IS10, rs)
2611}
2612
2613/// `Rd32=sub(Rt32,Rs32):sat`
2614///
2615/// Instruction Type: ALU32_3op
2616/// Execution Slots: SLOT0123
2617#[inline(always)]
2618#[cfg_attr(test, assert_instr(sub))]
2619#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2620pub unsafe fn Q6_R_sub_RR_sat(rt: i32, rs: i32) -> i32 {
2621    hexagon_A2_subsat(rt, rs)
2622}
2623
2624/// `Rd32=vaddh(Rs32,Rt32)`
2625///
2626/// Instruction Type: ALU32_3op
2627/// Execution Slots: SLOT0123
2628#[inline(always)]
2629#[cfg_attr(test, assert_instr(vaddh))]
2630#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2631pub unsafe fn Q6_R_vaddh_RR(rs: i32, rt: i32) -> i32 {
2632    hexagon_A2_svaddh(rs, rt)
2633}
2634
2635/// `Rd32=vaddh(Rs32,Rt32):sat`
2636///
2637/// Instruction Type: ALU32_3op
2638/// Execution Slots: SLOT0123
2639#[inline(always)]
2640#[cfg_attr(test, assert_instr(vaddh))]
2641#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2642pub unsafe fn Q6_R_vaddh_RR_sat(rs: i32, rt: i32) -> i32 {
2643    hexagon_A2_svaddhs(rs, rt)
2644}
2645
2646/// `Rd32=vadduh(Rs32,Rt32):sat`
2647///
2648/// Instruction Type: ALU32_3op
2649/// Execution Slots: SLOT0123
2650#[inline(always)]
2651#[cfg_attr(test, assert_instr(vadduh))]
2652#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2653pub unsafe fn Q6_R_vadduh_RR_sat(rs: i32, rt: i32) -> i32 {
2654    hexagon_A2_svadduhs(rs, rt)
2655}
2656
2657/// `Rd32=vavgh(Rs32,Rt32)`
2658///
2659/// Instruction Type: ALU32_3op
2660/// Execution Slots: SLOT0123
2661#[inline(always)]
2662#[cfg_attr(test, assert_instr(vavgh))]
2663#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2664pub unsafe fn Q6_R_vavgh_RR(rs: i32, rt: i32) -> i32 {
2665    hexagon_A2_svavgh(rs, rt)
2666}
2667
2668/// `Rd32=vavgh(Rs32,Rt32):rnd`
2669///
2670/// Instruction Type: ALU32_3op
2671/// Execution Slots: SLOT0123
2672#[inline(always)]
2673#[cfg_attr(test, assert_instr(vavgh))]
2674#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2675pub unsafe fn Q6_R_vavgh_RR_rnd(rs: i32, rt: i32) -> i32 {
2676    hexagon_A2_svavghs(rs, rt)
2677}
2678
2679/// `Rd32=vnavgh(Rt32,Rs32)`
2680///
2681/// Instruction Type: ALU32_3op
2682/// Execution Slots: SLOT0123
2683#[inline(always)]
2684#[cfg_attr(test, assert_instr(vnavgh))]
2685#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2686pub unsafe fn Q6_R_vnavgh_RR(rt: i32, rs: i32) -> i32 {
2687    hexagon_A2_svnavgh(rt, rs)
2688}
2689
2690/// `Rd32=vsubh(Rt32,Rs32)`
2691///
2692/// Instruction Type: ALU32_3op
2693/// Execution Slots: SLOT0123
2694#[inline(always)]
2695#[cfg_attr(test, assert_instr(vsubh))]
2696#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2697pub unsafe fn Q6_R_vsubh_RR(rt: i32, rs: i32) -> i32 {
2698    hexagon_A2_svsubh(rt, rs)
2699}
2700
2701/// `Rd32=vsubh(Rt32,Rs32):sat`
2702///
2703/// Instruction Type: ALU32_3op
2704/// Execution Slots: SLOT0123
2705#[inline(always)]
2706#[cfg_attr(test, assert_instr(vsubh))]
2707#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2708pub unsafe fn Q6_R_vsubh_RR_sat(rt: i32, rs: i32) -> i32 {
2709    hexagon_A2_svsubhs(rt, rs)
2710}
2711
2712/// `Rd32=vsubuh(Rt32,Rs32):sat`
2713///
2714/// Instruction Type: ALU32_3op
2715/// Execution Slots: SLOT0123
2716#[inline(always)]
2717#[cfg_attr(test, assert_instr(vsubuh))]
2718#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2719pub unsafe fn Q6_R_vsubuh_RR_sat(rt: i32, rs: i32) -> i32 {
2720    hexagon_A2_svsubuhs(rt, rs)
2721}
2722
2723/// `Rd32=swiz(Rs32)`
2724///
2725/// Instruction Type: S_2op
2726/// Execution Slots: SLOT23
2727#[inline(always)]
2728#[cfg_attr(test, assert_instr(swiz))]
2729#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2730pub unsafe fn Q6_R_swiz_R(rs: i32) -> i32 {
2731    hexagon_A2_swiz(rs)
2732}
2733
2734/// `Rd32=sxtb(Rs32)`
2735///
2736/// Instruction Type: ALU32_2op
2737/// Execution Slots: SLOT0123
2738#[inline(always)]
2739#[cfg_attr(test, assert_instr(sxtb))]
2740#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2741pub unsafe fn Q6_R_sxtb_R(rs: i32) -> i32 {
2742    hexagon_A2_sxtb(rs)
2743}
2744
2745/// `Rd32=sxth(Rs32)`
2746///
2747/// Instruction Type: ALU32_2op
2748/// Execution Slots: SLOT0123
2749#[inline(always)]
2750#[cfg_attr(test, assert_instr(sxth))]
2751#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2752pub unsafe fn Q6_R_sxth_R(rs: i32) -> i32 {
2753    hexagon_A2_sxth(rs)
2754}
2755
2756/// `Rdd32=sxtw(Rs32)`
2757///
2758/// Instruction Type: S_2op
2759/// Execution Slots: SLOT23
2760#[inline(always)]
2761#[cfg_attr(test, assert_instr(sxtw))]
2762#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2763pub unsafe fn Q6_P_sxtw_R(rs: i32) -> i64 {
2764    hexagon_A2_sxtw(rs)
2765}
2766
2767/// `Rd32=Rs32`
2768///
2769/// Instruction Type: ALU32_2op
2770/// Execution Slots: SLOT0123
2771#[inline(always)]
2772#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2773pub unsafe fn Q6_R_equals_R(rs: i32) -> i32 {
2774    hexagon_A2_tfr(rs)
2775}
2776
2777/// `Rx32.h=#u16`
2778///
2779/// Instruction Type: ALU32_2op
2780/// Execution Slots: SLOT0123
2781#[inline(always)]
2782#[rustc_legacy_const_generics(1)]
2783#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2784pub unsafe fn Q6_Rh_equals_I<const IU16: u32>(rx: i32) -> i32 {
2785    static_assert_uimm_bits!(IU16, 16);
2786    hexagon_A2_tfrih(rx, IU16 as i32)
2787}
2788
2789/// `Rx32.l=#u16`
2790///
2791/// Instruction Type: ALU32_2op
2792/// Execution Slots: SLOT0123
2793#[inline(always)]
2794#[rustc_legacy_const_generics(1)]
2795#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2796pub unsafe fn Q6_Rl_equals_I<const IU16: u32>(rx: i32) -> i32 {
2797    static_assert_uimm_bits!(IU16, 16);
2798    hexagon_A2_tfril(rx, IU16 as i32)
2799}
2800
2801/// `Rdd32=Rss32`
2802///
2803/// Instruction Type: ALU32_2op
2804/// Execution Slots: SLOT0123
2805#[inline(always)]
2806#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2807pub unsafe fn Q6_P_equals_P(rss: i64) -> i64 {
2808    hexagon_A2_tfrp(rss)
2809}
2810
2811/// `Rdd32=#s8`
2812///
2813/// Instruction Type: ALU64
2814/// Execution Slots: SLOT0123
2815#[inline(always)]
2816#[rustc_legacy_const_generics(0)]
2817#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2818pub unsafe fn Q6_P_equals_I<const IS8: i32>() -> i64 {
2819    static_assert_simm_bits!(IS8, 8);
2820    hexagon_A2_tfrpi(IS8)
2821}
2822
2823/// `Rd32=#s16`
2824///
2825/// Instruction Type: ALU32_2op
2826/// Execution Slots: SLOT0123
2827#[inline(always)]
2828#[rustc_legacy_const_generics(0)]
2829#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2830pub unsafe fn Q6_R_equals_I<const IS16: i32>() -> i32 {
2831    static_assert_simm_bits!(IS16, 16);
2832    hexagon_A2_tfrsi(IS16)
2833}
2834
2835/// `Rdd32=vabsh(Rss32)`
2836///
2837/// Instruction Type: S_2op
2838/// Execution Slots: SLOT23
2839#[inline(always)]
2840#[cfg_attr(test, assert_instr(vabsh))]
2841#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2842pub unsafe fn Q6_P_vabsh_P(rss: i64) -> i64 {
2843    hexagon_A2_vabsh(rss)
2844}
2845
2846/// `Rdd32=vabsh(Rss32):sat`
2847///
2848/// Instruction Type: S_2op
2849/// Execution Slots: SLOT23
2850#[inline(always)]
2851#[cfg_attr(test, assert_instr(vabsh))]
2852#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2853pub unsafe fn Q6_P_vabsh_P_sat(rss: i64) -> i64 {
2854    hexagon_A2_vabshsat(rss)
2855}
2856
2857/// `Rdd32=vabsw(Rss32)`
2858///
2859/// Instruction Type: S_2op
2860/// Execution Slots: SLOT23
2861#[inline(always)]
2862#[cfg_attr(test, assert_instr(vabsw))]
2863#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2864pub unsafe fn Q6_P_vabsw_P(rss: i64) -> i64 {
2865    hexagon_A2_vabsw(rss)
2866}
2867
2868/// `Rdd32=vabsw(Rss32):sat`
2869///
2870/// Instruction Type: S_2op
2871/// Execution Slots: SLOT23
2872#[inline(always)]
2873#[cfg_attr(test, assert_instr(vabsw))]
2874#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2875pub unsafe fn Q6_P_vabsw_P_sat(rss: i64) -> i64 {
2876    hexagon_A2_vabswsat(rss)
2877}
2878
2879/// `Rdd32=vaddb(Rss32,Rtt32)`
2880///
2881/// Instruction Type: MAPPING
2882/// Execution Slots: SLOT0123
2883#[inline(always)]
2884#[cfg_attr(test, assert_instr(vaddb))]
2885#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2886pub unsafe fn Q6_P_vaddb_PP(rss: i64, rtt: i64) -> i64 {
2887    hexagon_A2_vaddb_map(rss, rtt)
2888}
2889
2890/// `Rdd32=vaddh(Rss32,Rtt32)`
2891///
2892/// Instruction Type: ALU64
2893/// Execution Slots: SLOT23
2894#[inline(always)]
2895#[cfg_attr(test, assert_instr(vaddh))]
2896#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2897pub unsafe fn Q6_P_vaddh_PP(rss: i64, rtt: i64) -> i64 {
2898    hexagon_A2_vaddh(rss, rtt)
2899}
2900
2901/// `Rdd32=vaddh(Rss32,Rtt32):sat`
2902///
2903/// Instruction Type: ALU64
2904/// Execution Slots: SLOT23
2905#[inline(always)]
2906#[cfg_attr(test, assert_instr(vaddh))]
2907#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2908pub unsafe fn Q6_P_vaddh_PP_sat(rss: i64, rtt: i64) -> i64 {
2909    hexagon_A2_vaddhs(rss, rtt)
2910}
2911
2912/// `Rdd32=vaddub(Rss32,Rtt32)`
2913///
2914/// Instruction Type: ALU64
2915/// Execution Slots: SLOT23
2916#[inline(always)]
2917#[cfg_attr(test, assert_instr(vaddub))]
2918#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2919pub unsafe fn Q6_P_vaddub_PP(rss: i64, rtt: i64) -> i64 {
2920    hexagon_A2_vaddub(rss, rtt)
2921}
2922
2923/// `Rdd32=vaddub(Rss32,Rtt32):sat`
2924///
2925/// Instruction Type: ALU64
2926/// Execution Slots: SLOT23
2927#[inline(always)]
2928#[cfg_attr(test, assert_instr(vaddub))]
2929#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2930pub unsafe fn Q6_P_vaddub_PP_sat(rss: i64, rtt: i64) -> i64 {
2931    hexagon_A2_vaddubs(rss, rtt)
2932}
2933
2934/// `Rdd32=vadduh(Rss32,Rtt32):sat`
2935///
2936/// Instruction Type: ALU64
2937/// Execution Slots: SLOT23
2938#[inline(always)]
2939#[cfg_attr(test, assert_instr(vadduh))]
2940#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2941pub unsafe fn Q6_P_vadduh_PP_sat(rss: i64, rtt: i64) -> i64 {
2942    hexagon_A2_vadduhs(rss, rtt)
2943}
2944
2945/// `Rdd32=vaddw(Rss32,Rtt32)`
2946///
2947/// Instruction Type: ALU64
2948/// Execution Slots: SLOT23
2949#[inline(always)]
2950#[cfg_attr(test, assert_instr(vaddw))]
2951#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2952pub unsafe fn Q6_P_vaddw_PP(rss: i64, rtt: i64) -> i64 {
2953    hexagon_A2_vaddw(rss, rtt)
2954}
2955
2956/// `Rdd32=vaddw(Rss32,Rtt32):sat`
2957///
2958/// Instruction Type: ALU64
2959/// Execution Slots: SLOT23
2960#[inline(always)]
2961#[cfg_attr(test, assert_instr(vaddw))]
2962#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2963pub unsafe fn Q6_P_vaddw_PP_sat(rss: i64, rtt: i64) -> i64 {
2964    hexagon_A2_vaddws(rss, rtt)
2965}
2966
2967/// `Rdd32=vavgh(Rss32,Rtt32)`
2968///
2969/// Instruction Type: ALU64
2970/// Execution Slots: SLOT23
2971#[inline(always)]
2972#[cfg_attr(test, assert_instr(vavgh))]
2973#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2974pub unsafe fn Q6_P_vavgh_PP(rss: i64, rtt: i64) -> i64 {
2975    hexagon_A2_vavgh(rss, rtt)
2976}
2977
2978/// `Rdd32=vavgh(Rss32,Rtt32):crnd`
2979///
2980/// Instruction Type: ALU64
2981/// Execution Slots: SLOT23
2982#[inline(always)]
2983#[cfg_attr(test, assert_instr(vavgh))]
2984#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2985pub unsafe fn Q6_P_vavgh_PP_crnd(rss: i64, rtt: i64) -> i64 {
2986    hexagon_A2_vavghcr(rss, rtt)
2987}
2988
2989/// `Rdd32=vavgh(Rss32,Rtt32):rnd`
2990///
2991/// Instruction Type: ALU64
2992/// Execution Slots: SLOT23
2993#[inline(always)]
2994#[cfg_attr(test, assert_instr(vavgh))]
2995#[unstable(feature = "stdarch_hexagon", issue = "151523")]
2996pub unsafe fn Q6_P_vavgh_PP_rnd(rss: i64, rtt: i64) -> i64 {
2997    hexagon_A2_vavghr(rss, rtt)
2998}
2999
3000/// `Rdd32=vavgub(Rss32,Rtt32)`
3001///
3002/// Instruction Type: ALU64
3003/// Execution Slots: SLOT23
3004#[inline(always)]
3005#[cfg_attr(test, assert_instr(vavgub))]
3006#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3007pub unsafe fn Q6_P_vavgub_PP(rss: i64, rtt: i64) -> i64 {
3008    hexagon_A2_vavgub(rss, rtt)
3009}
3010
3011/// `Rdd32=vavgub(Rss32,Rtt32):rnd`
3012///
3013/// Instruction Type: ALU64
3014/// Execution Slots: SLOT23
3015#[inline(always)]
3016#[cfg_attr(test, assert_instr(vavgub))]
3017#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3018pub unsafe fn Q6_P_vavgub_PP_rnd(rss: i64, rtt: i64) -> i64 {
3019    hexagon_A2_vavgubr(rss, rtt)
3020}
3021
3022/// `Rdd32=vavguh(Rss32,Rtt32)`
3023///
3024/// Instruction Type: ALU64
3025/// Execution Slots: SLOT23
3026#[inline(always)]
3027#[cfg_attr(test, assert_instr(vavguh))]
3028#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3029pub unsafe fn Q6_P_vavguh_PP(rss: i64, rtt: i64) -> i64 {
3030    hexagon_A2_vavguh(rss, rtt)
3031}
3032
3033/// `Rdd32=vavguh(Rss32,Rtt32):rnd`
3034///
3035/// Instruction Type: ALU64
3036/// Execution Slots: SLOT23
3037#[inline(always)]
3038#[cfg_attr(test, assert_instr(vavguh))]
3039#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3040pub unsafe fn Q6_P_vavguh_PP_rnd(rss: i64, rtt: i64) -> i64 {
3041    hexagon_A2_vavguhr(rss, rtt)
3042}
3043
3044/// `Rdd32=vavguw(Rss32,Rtt32)`
3045///
3046/// Instruction Type: ALU64
3047/// Execution Slots: SLOT23
3048#[inline(always)]
3049#[cfg_attr(test, assert_instr(vavguw))]
3050#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3051pub unsafe fn Q6_P_vavguw_PP(rss: i64, rtt: i64) -> i64 {
3052    hexagon_A2_vavguw(rss, rtt)
3053}
3054
3055/// `Rdd32=vavguw(Rss32,Rtt32):rnd`
3056///
3057/// Instruction Type: ALU64
3058/// Execution Slots: SLOT23
3059#[inline(always)]
3060#[cfg_attr(test, assert_instr(vavguw))]
3061#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3062pub unsafe fn Q6_P_vavguw_PP_rnd(rss: i64, rtt: i64) -> i64 {
3063    hexagon_A2_vavguwr(rss, rtt)
3064}
3065
3066/// `Rdd32=vavgw(Rss32,Rtt32)`
3067///
3068/// Instruction Type: ALU64
3069/// Execution Slots: SLOT23
3070#[inline(always)]
3071#[cfg_attr(test, assert_instr(vavgw))]
3072#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3073pub unsafe fn Q6_P_vavgw_PP(rss: i64, rtt: i64) -> i64 {
3074    hexagon_A2_vavgw(rss, rtt)
3075}
3076
3077/// `Rdd32=vavgw(Rss32,Rtt32):crnd`
3078///
3079/// Instruction Type: ALU64
3080/// Execution Slots: SLOT23
3081#[inline(always)]
3082#[cfg_attr(test, assert_instr(vavgw))]
3083#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3084pub unsafe fn Q6_P_vavgw_PP_crnd(rss: i64, rtt: i64) -> i64 {
3085    hexagon_A2_vavgwcr(rss, rtt)
3086}
3087
3088/// `Rdd32=vavgw(Rss32,Rtt32):rnd`
3089///
3090/// Instruction Type: ALU64
3091/// Execution Slots: SLOT23
3092#[inline(always)]
3093#[cfg_attr(test, assert_instr(vavgw))]
3094#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3095pub unsafe fn Q6_P_vavgw_PP_rnd(rss: i64, rtt: i64) -> i64 {
3096    hexagon_A2_vavgwr(rss, rtt)
3097}
3098
3099/// `Pd4=vcmpb.eq(Rss32,Rtt32)`
3100///
3101/// Instruction Type: ALU64
3102/// Execution Slots: SLOT23
3103#[inline(always)]
3104#[cfg_attr(test, assert_instr(vcmpb))]
3105#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3106pub unsafe fn Q6_p_vcmpb_eq_PP(rss: i64, rtt: i64) -> i32 {
3107    hexagon_A2_vcmpbeq(rss, rtt)
3108}
3109
3110/// `Pd4=vcmpb.gtu(Rss32,Rtt32)`
3111///
3112/// Instruction Type: ALU64
3113/// Execution Slots: SLOT23
3114#[inline(always)]
3115#[cfg_attr(test, assert_instr(vcmpb))]
3116#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3117pub unsafe fn Q6_p_vcmpb_gtu_PP(rss: i64, rtt: i64) -> i32 {
3118    hexagon_A2_vcmpbgtu(rss, rtt)
3119}
3120
3121/// `Pd4=vcmph.eq(Rss32,Rtt32)`
3122///
3123/// Instruction Type: ALU64
3124/// Execution Slots: SLOT23
3125#[inline(always)]
3126#[cfg_attr(test, assert_instr(vcmph))]
3127#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3128pub unsafe fn Q6_p_vcmph_eq_PP(rss: i64, rtt: i64) -> i32 {
3129    hexagon_A2_vcmpheq(rss, rtt)
3130}
3131
3132/// `Pd4=vcmph.gt(Rss32,Rtt32)`
3133///
3134/// Instruction Type: ALU64
3135/// Execution Slots: SLOT23
3136#[inline(always)]
3137#[cfg_attr(test, assert_instr(vcmph))]
3138#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3139pub unsafe fn Q6_p_vcmph_gt_PP(rss: i64, rtt: i64) -> i32 {
3140    hexagon_A2_vcmphgt(rss, rtt)
3141}
3142
3143/// `Pd4=vcmph.gtu(Rss32,Rtt32)`
3144///
3145/// Instruction Type: ALU64
3146/// Execution Slots: SLOT23
3147#[inline(always)]
3148#[cfg_attr(test, assert_instr(vcmph))]
3149#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3150pub unsafe fn Q6_p_vcmph_gtu_PP(rss: i64, rtt: i64) -> i32 {
3151    hexagon_A2_vcmphgtu(rss, rtt)
3152}
3153
3154/// `Pd4=vcmpw.eq(Rss32,Rtt32)`
3155///
3156/// Instruction Type: ALU64
3157/// Execution Slots: SLOT23
3158#[inline(always)]
3159#[cfg_attr(test, assert_instr(vcmpw))]
3160#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3161pub unsafe fn Q6_p_vcmpw_eq_PP(rss: i64, rtt: i64) -> i32 {
3162    hexagon_A2_vcmpweq(rss, rtt)
3163}
3164
3165/// `Pd4=vcmpw.gt(Rss32,Rtt32)`
3166///
3167/// Instruction Type: ALU64
3168/// Execution Slots: SLOT23
3169#[inline(always)]
3170#[cfg_attr(test, assert_instr(vcmpw))]
3171#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3172pub unsafe fn Q6_p_vcmpw_gt_PP(rss: i64, rtt: i64) -> i32 {
3173    hexagon_A2_vcmpwgt(rss, rtt)
3174}
3175
3176/// `Pd4=vcmpw.gtu(Rss32,Rtt32)`
3177///
3178/// Instruction Type: ALU64
3179/// Execution Slots: SLOT23
3180#[inline(always)]
3181#[cfg_attr(test, assert_instr(vcmpw))]
3182#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3183pub unsafe fn Q6_p_vcmpw_gtu_PP(rss: i64, rtt: i64) -> i32 {
3184    hexagon_A2_vcmpwgtu(rss, rtt)
3185}
3186
3187/// `Rdd32=vconj(Rss32):sat`
3188///
3189/// Instruction Type: S_2op
3190/// Execution Slots: SLOT23
3191#[inline(always)]
3192#[cfg_attr(test, assert_instr(vconj))]
3193#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3194pub unsafe fn Q6_P_vconj_P_sat(rss: i64) -> i64 {
3195    hexagon_A2_vconj(rss)
3196}
3197
3198/// `Rdd32=vmaxb(Rtt32,Rss32)`
3199///
3200/// Instruction Type: ALU64
3201/// Execution Slots: SLOT23
3202#[inline(always)]
3203#[cfg_attr(test, assert_instr(vmaxb))]
3204#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3205pub unsafe fn Q6_P_vmaxb_PP(rtt: i64, rss: i64) -> i64 {
3206    hexagon_A2_vmaxb(rtt, rss)
3207}
3208
3209/// `Rdd32=vmaxh(Rtt32,Rss32)`
3210///
3211/// Instruction Type: ALU64
3212/// Execution Slots: SLOT23
3213#[inline(always)]
3214#[cfg_attr(test, assert_instr(vmaxh))]
3215#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3216pub unsafe fn Q6_P_vmaxh_PP(rtt: i64, rss: i64) -> i64 {
3217    hexagon_A2_vmaxh(rtt, rss)
3218}
3219
3220/// `Rdd32=vmaxub(Rtt32,Rss32)`
3221///
3222/// Instruction Type: ALU64
3223/// Execution Slots: SLOT23
3224#[inline(always)]
3225#[cfg_attr(test, assert_instr(vmaxub))]
3226#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3227pub unsafe fn Q6_P_vmaxub_PP(rtt: i64, rss: i64) -> i64 {
3228    hexagon_A2_vmaxub(rtt, rss)
3229}
3230
3231/// `Rdd32=vmaxuh(Rtt32,Rss32)`
3232///
3233/// Instruction Type: ALU64
3234/// Execution Slots: SLOT23
3235#[inline(always)]
3236#[cfg_attr(test, assert_instr(vmaxuh))]
3237#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3238pub unsafe fn Q6_P_vmaxuh_PP(rtt: i64, rss: i64) -> i64 {
3239    hexagon_A2_vmaxuh(rtt, rss)
3240}
3241
3242/// `Rdd32=vmaxuw(Rtt32,Rss32)`
3243///
3244/// Instruction Type: ALU64
3245/// Execution Slots: SLOT23
3246#[inline(always)]
3247#[cfg_attr(test, assert_instr(vmaxuw))]
3248#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3249pub unsafe fn Q6_P_vmaxuw_PP(rtt: i64, rss: i64) -> i64 {
3250    hexagon_A2_vmaxuw(rtt, rss)
3251}
3252
3253/// `Rdd32=vmaxw(Rtt32,Rss32)`
3254///
3255/// Instruction Type: ALU64
3256/// Execution Slots: SLOT23
3257#[inline(always)]
3258#[cfg_attr(test, assert_instr(vmaxw))]
3259#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3260pub unsafe fn Q6_P_vmaxw_PP(rtt: i64, rss: i64) -> i64 {
3261    hexagon_A2_vmaxw(rtt, rss)
3262}
3263
3264/// `Rdd32=vminb(Rtt32,Rss32)`
3265///
3266/// Instruction Type: ALU64
3267/// Execution Slots: SLOT23
3268#[inline(always)]
3269#[cfg_attr(test, assert_instr(vminb))]
3270#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3271pub unsafe fn Q6_P_vminb_PP(rtt: i64, rss: i64) -> i64 {
3272    hexagon_A2_vminb(rtt, rss)
3273}
3274
3275/// `Rdd32=vminh(Rtt32,Rss32)`
3276///
3277/// Instruction Type: ALU64
3278/// Execution Slots: SLOT23
3279#[inline(always)]
3280#[cfg_attr(test, assert_instr(vminh))]
3281#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3282pub unsafe fn Q6_P_vminh_PP(rtt: i64, rss: i64) -> i64 {
3283    hexagon_A2_vminh(rtt, rss)
3284}
3285
3286/// `Rdd32=vminub(Rtt32,Rss32)`
3287///
3288/// Instruction Type: ALU64
3289/// Execution Slots: SLOT23
3290#[inline(always)]
3291#[cfg_attr(test, assert_instr(vminub))]
3292#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3293pub unsafe fn Q6_P_vminub_PP(rtt: i64, rss: i64) -> i64 {
3294    hexagon_A2_vminub(rtt, rss)
3295}
3296
3297/// `Rdd32=vminuh(Rtt32,Rss32)`
3298///
3299/// Instruction Type: ALU64
3300/// Execution Slots: SLOT23
3301#[inline(always)]
3302#[cfg_attr(test, assert_instr(vminuh))]
3303#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3304pub unsafe fn Q6_P_vminuh_PP(rtt: i64, rss: i64) -> i64 {
3305    hexagon_A2_vminuh(rtt, rss)
3306}
3307
3308/// `Rdd32=vminuw(Rtt32,Rss32)`
3309///
3310/// Instruction Type: ALU64
3311/// Execution Slots: SLOT23
3312#[inline(always)]
3313#[cfg_attr(test, assert_instr(vminuw))]
3314#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3315pub unsafe fn Q6_P_vminuw_PP(rtt: i64, rss: i64) -> i64 {
3316    hexagon_A2_vminuw(rtt, rss)
3317}
3318
3319/// `Rdd32=vminw(Rtt32,Rss32)`
3320///
3321/// Instruction Type: ALU64
3322/// Execution Slots: SLOT23
3323#[inline(always)]
3324#[cfg_attr(test, assert_instr(vminw))]
3325#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3326pub unsafe fn Q6_P_vminw_PP(rtt: i64, rss: i64) -> i64 {
3327    hexagon_A2_vminw(rtt, rss)
3328}
3329
3330/// `Rdd32=vnavgh(Rtt32,Rss32)`
3331///
3332/// Instruction Type: ALU64
3333/// Execution Slots: SLOT23
3334#[inline(always)]
3335#[cfg_attr(test, assert_instr(vnavgh))]
3336#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3337pub unsafe fn Q6_P_vnavgh_PP(rtt: i64, rss: i64) -> i64 {
3338    hexagon_A2_vnavgh(rtt, rss)
3339}
3340
3341/// `Rdd32=vnavgh(Rtt32,Rss32):crnd:sat`
3342///
3343/// Instruction Type: ALU64
3344/// Execution Slots: SLOT23
3345#[inline(always)]
3346#[cfg_attr(test, assert_instr(vnavgh))]
3347#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3348pub unsafe fn Q6_P_vnavgh_PP_crnd_sat(rtt: i64, rss: i64) -> i64 {
3349    hexagon_A2_vnavghcr(rtt, rss)
3350}
3351
3352/// `Rdd32=vnavgh(Rtt32,Rss32):rnd:sat`
3353///
3354/// Instruction Type: ALU64
3355/// Execution Slots: SLOT23
3356#[inline(always)]
3357#[cfg_attr(test, assert_instr(vnavgh))]
3358#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3359pub unsafe fn Q6_P_vnavgh_PP_rnd_sat(rtt: i64, rss: i64) -> i64 {
3360    hexagon_A2_vnavghr(rtt, rss)
3361}
3362
3363/// `Rdd32=vnavgw(Rtt32,Rss32)`
3364///
3365/// Instruction Type: ALU64
3366/// Execution Slots: SLOT23
3367#[inline(always)]
3368#[cfg_attr(test, assert_instr(vnavgw))]
3369#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3370pub unsafe fn Q6_P_vnavgw_PP(rtt: i64, rss: i64) -> i64 {
3371    hexagon_A2_vnavgw(rtt, rss)
3372}
3373
3374/// `Rdd32=vnavgw(Rtt32,Rss32):crnd:sat`
3375///
3376/// Instruction Type: ALU64
3377/// Execution Slots: SLOT23
3378#[inline(always)]
3379#[cfg_attr(test, assert_instr(vnavgw))]
3380#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3381pub unsafe fn Q6_P_vnavgw_PP_crnd_sat(rtt: i64, rss: i64) -> i64 {
3382    hexagon_A2_vnavgwcr(rtt, rss)
3383}
3384
3385/// `Rdd32=vnavgw(Rtt32,Rss32):rnd:sat`
3386///
3387/// Instruction Type: ALU64
3388/// Execution Slots: SLOT23
3389#[inline(always)]
3390#[cfg_attr(test, assert_instr(vnavgw))]
3391#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3392pub unsafe fn Q6_P_vnavgw_PP_rnd_sat(rtt: i64, rss: i64) -> i64 {
3393    hexagon_A2_vnavgwr(rtt, rss)
3394}
3395
3396/// `Rdd32=vraddub(Rss32,Rtt32)`
3397///
3398/// Instruction Type: M
3399/// Execution Slots: SLOT23
3400#[inline(always)]
3401#[cfg_attr(test, assert_instr(vraddub))]
3402#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3403pub unsafe fn Q6_P_vraddub_PP(rss: i64, rtt: i64) -> i64 {
3404    hexagon_A2_vraddub(rss, rtt)
3405}
3406
3407/// `Rxx32+=vraddub(Rss32,Rtt32)`
3408///
3409/// Instruction Type: M
3410/// Execution Slots: SLOT23
3411#[inline(always)]
3412#[cfg_attr(test, assert_instr(vraddub))]
3413#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3414pub unsafe fn Q6_P_vraddubacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
3415    hexagon_A2_vraddub_acc(rxx, rss, rtt)
3416}
3417
3418/// `Rdd32=vrsadub(Rss32,Rtt32)`
3419///
3420/// Instruction Type: M
3421/// Execution Slots: SLOT23
3422#[inline(always)]
3423#[cfg_attr(test, assert_instr(vrsadub))]
3424#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3425pub unsafe fn Q6_P_vrsadub_PP(rss: i64, rtt: i64) -> i64 {
3426    hexagon_A2_vrsadub(rss, rtt)
3427}
3428
3429/// `Rxx32+=vrsadub(Rss32,Rtt32)`
3430///
3431/// Instruction Type: M
3432/// Execution Slots: SLOT23
3433#[inline(always)]
3434#[cfg_attr(test, assert_instr(vrsadub))]
3435#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3436pub unsafe fn Q6_P_vrsadubacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
3437    hexagon_A2_vrsadub_acc(rxx, rss, rtt)
3438}
3439
3440/// `Rdd32=vsubb(Rss32,Rtt32)`
3441///
3442/// Instruction Type: MAPPING
3443/// Execution Slots: SLOT0123
3444#[inline(always)]
3445#[cfg_attr(test, assert_instr(vsubb))]
3446#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3447pub unsafe fn Q6_P_vsubb_PP(rss: i64, rtt: i64) -> i64 {
3448    hexagon_A2_vsubb_map(rss, rtt)
3449}
3450
3451/// `Rdd32=vsubh(Rtt32,Rss32)`
3452///
3453/// Instruction Type: ALU64
3454/// Execution Slots: SLOT23
3455#[inline(always)]
3456#[cfg_attr(test, assert_instr(vsubh))]
3457#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3458pub unsafe fn Q6_P_vsubh_PP(rtt: i64, rss: i64) -> i64 {
3459    hexagon_A2_vsubh(rtt, rss)
3460}
3461
3462/// `Rdd32=vsubh(Rtt32,Rss32):sat`
3463///
3464/// Instruction Type: ALU64
3465/// Execution Slots: SLOT23
3466#[inline(always)]
3467#[cfg_attr(test, assert_instr(vsubh))]
3468#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3469pub unsafe fn Q6_P_vsubh_PP_sat(rtt: i64, rss: i64) -> i64 {
3470    hexagon_A2_vsubhs(rtt, rss)
3471}
3472
3473/// `Rdd32=vsubub(Rtt32,Rss32)`
3474///
3475/// Instruction Type: ALU64
3476/// Execution Slots: SLOT23
3477#[inline(always)]
3478#[cfg_attr(test, assert_instr(vsubub))]
3479#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3480pub unsafe fn Q6_P_vsubub_PP(rtt: i64, rss: i64) -> i64 {
3481    hexagon_A2_vsubub(rtt, rss)
3482}
3483
3484/// `Rdd32=vsubub(Rtt32,Rss32):sat`
3485///
3486/// Instruction Type: ALU64
3487/// Execution Slots: SLOT23
3488#[inline(always)]
3489#[cfg_attr(test, assert_instr(vsubub))]
3490#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3491pub unsafe fn Q6_P_vsubub_PP_sat(rtt: i64, rss: i64) -> i64 {
3492    hexagon_A2_vsububs(rtt, rss)
3493}
3494
3495/// `Rdd32=vsubuh(Rtt32,Rss32):sat`
3496///
3497/// Instruction Type: ALU64
3498/// Execution Slots: SLOT23
3499#[inline(always)]
3500#[cfg_attr(test, assert_instr(vsubuh))]
3501#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3502pub unsafe fn Q6_P_vsubuh_PP_sat(rtt: i64, rss: i64) -> i64 {
3503    hexagon_A2_vsubuhs(rtt, rss)
3504}
3505
3506/// `Rdd32=vsubw(Rtt32,Rss32)`
3507///
3508/// Instruction Type: ALU64
3509/// Execution Slots: SLOT23
3510#[inline(always)]
3511#[cfg_attr(test, assert_instr(vsubw))]
3512#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3513pub unsafe fn Q6_P_vsubw_PP(rtt: i64, rss: i64) -> i64 {
3514    hexagon_A2_vsubw(rtt, rss)
3515}
3516
3517/// `Rdd32=vsubw(Rtt32,Rss32):sat`
3518///
3519/// Instruction Type: ALU64
3520/// Execution Slots: SLOT23
3521#[inline(always)]
3522#[cfg_attr(test, assert_instr(vsubw))]
3523#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3524pub unsafe fn Q6_P_vsubw_PP_sat(rtt: i64, rss: i64) -> i64 {
3525    hexagon_A2_vsubws(rtt, rss)
3526}
3527
3528/// `Rd32=xor(Rs32,Rt32)`
3529///
3530/// Instruction Type: ALU32_3op
3531/// Execution Slots: SLOT0123
3532#[inline(always)]
3533#[cfg_attr(test, assert_instr(xor))]
3534#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3535pub unsafe fn Q6_R_xor_RR(rs: i32, rt: i32) -> i32 {
3536    hexagon_A2_xor(rs, rt)
3537}
3538
3539/// `Rdd32=xor(Rss32,Rtt32)`
3540///
3541/// Instruction Type: ALU64
3542/// Execution Slots: SLOT23
3543#[inline(always)]
3544#[cfg_attr(test, assert_instr(xor))]
3545#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3546pub unsafe fn Q6_P_xor_PP(rss: i64, rtt: i64) -> i64 {
3547    hexagon_A2_xorp(rss, rtt)
3548}
3549
3550/// `Rd32=zxtb(Rs32)`
3551///
3552/// Instruction Type: ALU32_2op
3553/// Execution Slots: SLOT0123
3554#[inline(always)]
3555#[cfg_attr(test, assert_instr(zxtb))]
3556#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3557pub unsafe fn Q6_R_zxtb_R(rs: i32) -> i32 {
3558    hexagon_A2_zxtb(rs)
3559}
3560
3561/// `Rd32=zxth(Rs32)`
3562///
3563/// Instruction Type: ALU32_2op
3564/// Execution Slots: SLOT0123
3565#[inline(always)]
3566#[cfg_attr(test, assert_instr(zxth))]
3567#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3568pub unsafe fn Q6_R_zxth_R(rs: i32) -> i32 {
3569    hexagon_A2_zxth(rs)
3570}
3571
3572/// `Rd32=and(Rt32,~Rs32)`
3573///
3574/// Instruction Type: ALU32_3op
3575/// Execution Slots: SLOT0123
3576#[inline(always)]
3577#[cfg_attr(test, assert_instr(and))]
3578#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3579pub unsafe fn Q6_R_and_RnR(rt: i32, rs: i32) -> i32 {
3580    hexagon_A4_andn(rt, rs)
3581}
3582
3583/// `Rdd32=and(Rtt32,~Rss32)`
3584///
3585/// Instruction Type: ALU64
3586/// Execution Slots: SLOT23
3587#[inline(always)]
3588#[cfg_attr(test, assert_instr(and))]
3589#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3590pub unsafe fn Q6_P_and_PnP(rtt: i64, rss: i64) -> i64 {
3591    hexagon_A4_andnp(rtt, rss)
3592}
3593
3594/// `Rdd32=bitsplit(Rs32,Rt32)`
3595///
3596/// Instruction Type: ALU64
3597/// Execution Slots: SLOT23
3598#[inline(always)]
3599#[cfg_attr(test, assert_instr(bitsplit))]
3600#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3601pub unsafe fn Q6_P_bitsplit_RR(rs: i32, rt: i32) -> i64 {
3602    hexagon_A4_bitsplit(rs, rt)
3603}
3604
3605/// `Rdd32=bitsplit(Rs32,#u5)`
3606///
3607/// Instruction Type: S_2op
3608/// Execution Slots: SLOT23
3609#[inline(always)]
3610#[rustc_legacy_const_generics(1)]
3611#[cfg_attr(test, assert_instr(bitsplit, IU5 = 0))]
3612#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3613pub unsafe fn Q6_P_bitsplit_RI<const IU5: u32>(rs: i32) -> i64 {
3614    static_assert_uimm_bits!(IU5, 5);
3615    hexagon_A4_bitspliti(rs, IU5 as i32)
3616}
3617
3618/// `Pd4=boundscheck(Rs32,Rtt32)`
3619///
3620/// Instruction Type: ALU64
3621/// Execution Slots: SLOT0123
3622#[inline(always)]
3623#[cfg_attr(test, assert_instr(boundscheck))]
3624#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3625pub unsafe fn Q6_p_boundscheck_RP(rs: i32, rtt: i64) -> i32 {
3626    hexagon_A4_boundscheck(rs, rtt)
3627}
3628
3629/// `Pd4=cmpb.eq(Rs32,Rt32)`
3630///
3631/// Instruction Type: S_3op
3632/// Execution Slots: SLOT23
3633#[inline(always)]
3634#[cfg_attr(test, assert_instr(cmpb))]
3635#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3636pub unsafe fn Q6_p_cmpb_eq_RR(rs: i32, rt: i32) -> i32 {
3637    hexagon_A4_cmpbeq(rs, rt)
3638}
3639
3640/// `Pd4=cmpb.eq(Rs32,#u8)`
3641///
3642/// Instruction Type: ALU64
3643/// Execution Slots: SLOT23
3644#[inline(always)]
3645#[rustc_legacy_const_generics(1)]
3646#[cfg_attr(test, assert_instr(cmpb, IU8 = 0))]
3647#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3648pub unsafe fn Q6_p_cmpb_eq_RI<const IU8: u32>(rs: i32) -> i32 {
3649    static_assert_uimm_bits!(IU8, 8);
3650    hexagon_A4_cmpbeqi(rs, IU8 as i32)
3651}
3652
3653/// `Pd4=cmpb.gt(Rs32,Rt32)`
3654///
3655/// Instruction Type: S_3op
3656/// Execution Slots: SLOT23
3657#[inline(always)]
3658#[cfg_attr(test, assert_instr(cmpb))]
3659#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3660pub unsafe fn Q6_p_cmpb_gt_RR(rs: i32, rt: i32) -> i32 {
3661    hexagon_A4_cmpbgt(rs, rt)
3662}
3663
3664/// `Pd4=cmpb.gt(Rs32,#s8)`
3665///
3666/// Instruction Type: ALU64
3667/// Execution Slots: SLOT23
3668#[inline(always)]
3669#[rustc_legacy_const_generics(1)]
3670#[cfg_attr(test, assert_instr(cmpb, IS8 = 0))]
3671#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3672pub unsafe fn Q6_p_cmpb_gt_RI<const IS8: i32>(rs: i32) -> i32 {
3673    static_assert_simm_bits!(IS8, 8);
3674    hexagon_A4_cmpbgti(rs, IS8)
3675}
3676
3677/// `Pd4=cmpb.gtu(Rs32,Rt32)`
3678///
3679/// Instruction Type: S_3op
3680/// Execution Slots: SLOT23
3681#[inline(always)]
3682#[cfg_attr(test, assert_instr(cmpb))]
3683#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3684pub unsafe fn Q6_p_cmpb_gtu_RR(rs: i32, rt: i32) -> i32 {
3685    hexagon_A4_cmpbgtu(rs, rt)
3686}
3687
3688/// `Pd4=cmpb.gtu(Rs32,#u7)`
3689///
3690/// Instruction Type: ALU64
3691/// Execution Slots: SLOT23
3692#[inline(always)]
3693#[rustc_legacy_const_generics(1)]
3694#[cfg_attr(test, assert_instr(cmpb, IU7 = 0))]
3695#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3696pub unsafe fn Q6_p_cmpb_gtu_RI<const IU7: u32>(rs: i32) -> i32 {
3697    static_assert_uimm_bits!(IU7, 7);
3698    hexagon_A4_cmpbgtui(rs, IU7 as i32)
3699}
3700
3701/// `Pd4=cmph.eq(Rs32,Rt32)`
3702///
3703/// Instruction Type: S_3op
3704/// Execution Slots: SLOT23
3705#[inline(always)]
3706#[cfg_attr(test, assert_instr(cmph))]
3707#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3708pub unsafe fn Q6_p_cmph_eq_RR(rs: i32, rt: i32) -> i32 {
3709    hexagon_A4_cmpheq(rs, rt)
3710}
3711
3712/// `Pd4=cmph.eq(Rs32,#s8)`
3713///
3714/// Instruction Type: ALU64
3715/// Execution Slots: SLOT23
3716#[inline(always)]
3717#[rustc_legacy_const_generics(1)]
3718#[cfg_attr(test, assert_instr(cmph, IS8 = 0))]
3719#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3720pub unsafe fn Q6_p_cmph_eq_RI<const IS8: i32>(rs: i32) -> i32 {
3721    static_assert_simm_bits!(IS8, 8);
3722    hexagon_A4_cmpheqi(rs, IS8)
3723}
3724
3725/// `Pd4=cmph.gt(Rs32,Rt32)`
3726///
3727/// Instruction Type: S_3op
3728/// Execution Slots: SLOT23
3729#[inline(always)]
3730#[cfg_attr(test, assert_instr(cmph))]
3731#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3732pub unsafe fn Q6_p_cmph_gt_RR(rs: i32, rt: i32) -> i32 {
3733    hexagon_A4_cmphgt(rs, rt)
3734}
3735
3736/// `Pd4=cmph.gt(Rs32,#s8)`
3737///
3738/// Instruction Type: ALU64
3739/// Execution Slots: SLOT23
3740#[inline(always)]
3741#[rustc_legacy_const_generics(1)]
3742#[cfg_attr(test, assert_instr(cmph, IS8 = 0))]
3743#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3744pub unsafe fn Q6_p_cmph_gt_RI<const IS8: i32>(rs: i32) -> i32 {
3745    static_assert_simm_bits!(IS8, 8);
3746    hexagon_A4_cmphgti(rs, IS8)
3747}
3748
3749/// `Pd4=cmph.gtu(Rs32,Rt32)`
3750///
3751/// Instruction Type: S_3op
3752/// Execution Slots: SLOT23
3753#[inline(always)]
3754#[cfg_attr(test, assert_instr(cmph))]
3755#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3756pub unsafe fn Q6_p_cmph_gtu_RR(rs: i32, rt: i32) -> i32 {
3757    hexagon_A4_cmphgtu(rs, rt)
3758}
3759
3760/// `Pd4=cmph.gtu(Rs32,#u7)`
3761///
3762/// Instruction Type: ALU64
3763/// Execution Slots: SLOT23
3764#[inline(always)]
3765#[rustc_legacy_const_generics(1)]
3766#[cfg_attr(test, assert_instr(cmph, IU7 = 0))]
3767#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3768pub unsafe fn Q6_p_cmph_gtu_RI<const IU7: u32>(rs: i32) -> i32 {
3769    static_assert_uimm_bits!(IU7, 7);
3770    hexagon_A4_cmphgtui(rs, IU7 as i32)
3771}
3772
3773/// `Rdd32=combine(#s8,Rs32)`
3774///
3775/// Instruction Type: ALU32_2op
3776/// Execution Slots: SLOT0123
3777#[inline(always)]
3778#[rustc_legacy_const_generics(0)]
3779#[cfg_attr(test, assert_instr(combine, IS8 = 0))]
3780#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3781pub unsafe fn Q6_P_combine_IR<const IS8: i32>(rs: i32) -> i64 {
3782    static_assert_simm_bits!(IS8, 8);
3783    hexagon_A4_combineir(IS8, rs)
3784}
3785
3786/// `Rdd32=combine(Rs32,#s8)`
3787///
3788/// Instruction Type: ALU32_2op
3789/// Execution Slots: SLOT0123
3790#[inline(always)]
3791#[rustc_legacy_const_generics(1)]
3792#[cfg_attr(test, assert_instr(combine, IS8 = 0))]
3793#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3794pub unsafe fn Q6_P_combine_RI<const IS8: i32>(rs: i32) -> i64 {
3795    static_assert_simm_bits!(IS8, 8);
3796    hexagon_A4_combineri(rs, IS8)
3797}
3798
3799/// `Rd32=cround(Rs32,#u5)`
3800///
3801/// Instruction Type: S_2op
3802/// Execution Slots: SLOT23
3803#[inline(always)]
3804#[rustc_legacy_const_generics(1)]
3805#[cfg_attr(test, assert_instr(cround, IU5 = 0))]
3806#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3807pub unsafe fn Q6_R_cround_RI<const IU5: u32>(rs: i32) -> i32 {
3808    static_assert_uimm_bits!(IU5, 5);
3809    hexagon_A4_cround_ri(rs, IU5 as i32)
3810}
3811
3812/// `Rd32=cround(Rs32,Rt32)`
3813///
3814/// Instruction Type: S_3op
3815/// Execution Slots: SLOT23
3816#[inline(always)]
3817#[cfg_attr(test, assert_instr(cround))]
3818#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3819pub unsafe fn Q6_R_cround_RR(rs: i32, rt: i32) -> i32 {
3820    hexagon_A4_cround_rr(rs, rt)
3821}
3822
3823/// `Rd32=modwrap(Rs32,Rt32)`
3824///
3825/// Instruction Type: ALU64
3826/// Execution Slots: SLOT23
3827#[inline(always)]
3828#[cfg_attr(test, assert_instr(modwrap))]
3829#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3830pub unsafe fn Q6_R_modwrap_RR(rs: i32, rt: i32) -> i32 {
3831    hexagon_A4_modwrapu(rs, rt)
3832}
3833
3834/// `Rd32=or(Rt32,~Rs32)`
3835///
3836/// Instruction Type: ALU32_3op
3837/// Execution Slots: SLOT0123
3838#[inline(always)]
3839#[cfg_attr(test, assert_instr(or))]
3840#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3841pub unsafe fn Q6_R_or_RnR(rt: i32, rs: i32) -> i32 {
3842    hexagon_A4_orn(rt, rs)
3843}
3844
3845/// `Rdd32=or(Rtt32,~Rss32)`
3846///
3847/// Instruction Type: ALU64
3848/// Execution Slots: SLOT23
3849#[inline(always)]
3850#[cfg_attr(test, assert_instr(or))]
3851#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3852pub unsafe fn Q6_P_or_PnP(rtt: i64, rss: i64) -> i64 {
3853    hexagon_A4_ornp(rtt, rss)
3854}
3855
3856/// `Rd32=cmp.eq(Rs32,Rt32)`
3857///
3858/// Instruction Type: ALU32_3op
3859/// Execution Slots: SLOT0123
3860#[inline(always)]
3861#[cfg_attr(test, assert_instr(cmp))]
3862#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3863pub unsafe fn Q6_R_cmp_eq_RR(rs: i32, rt: i32) -> i32 {
3864    hexagon_A4_rcmpeq(rs, rt)
3865}
3866
3867/// `Rd32=cmp.eq(Rs32,#s8)`
3868///
3869/// Instruction Type: ALU32_2op
3870/// Execution Slots: SLOT0123
3871#[inline(always)]
3872#[rustc_legacy_const_generics(1)]
3873#[cfg_attr(test, assert_instr(cmp, IS8 = 0))]
3874#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3875pub unsafe fn Q6_R_cmp_eq_RI<const IS8: i32>(rs: i32) -> i32 {
3876    static_assert_simm_bits!(IS8, 8);
3877    hexagon_A4_rcmpeqi(rs, IS8)
3878}
3879
3880/// `Rd32=!cmp.eq(Rs32,Rt32)`
3881///
3882/// Instruction Type: ALU32_3op
3883/// Execution Slots: SLOT0123
3884#[inline(always)]
3885#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3886pub unsafe fn Q6_R_not_cmp_eq_RR(rs: i32, rt: i32) -> i32 {
3887    hexagon_A4_rcmpneq(rs, rt)
3888}
3889
3890/// `Rd32=!cmp.eq(Rs32,#s8)`
3891///
3892/// Instruction Type: ALU32_2op
3893/// Execution Slots: SLOT0123
3894#[inline(always)]
3895#[rustc_legacy_const_generics(1)]
3896#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3897pub unsafe fn Q6_R_not_cmp_eq_RI<const IS8: i32>(rs: i32) -> i32 {
3898    static_assert_simm_bits!(IS8, 8);
3899    hexagon_A4_rcmpneqi(rs, IS8)
3900}
3901
3902/// `Rd32=round(Rs32,#u5)`
3903///
3904/// Instruction Type: S_2op
3905/// Execution Slots: SLOT23
3906#[inline(always)]
3907#[rustc_legacy_const_generics(1)]
3908#[cfg_attr(test, assert_instr(round, IU5 = 0))]
3909#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3910pub unsafe fn Q6_R_round_RI<const IU5: u32>(rs: i32) -> i32 {
3911    static_assert_uimm_bits!(IU5, 5);
3912    hexagon_A4_round_ri(rs, IU5 as i32)
3913}
3914
3915/// `Rd32=round(Rs32,#u5):sat`
3916///
3917/// Instruction Type: S_2op
3918/// Execution Slots: SLOT23
3919#[inline(always)]
3920#[rustc_legacy_const_generics(1)]
3921#[cfg_attr(test, assert_instr(round, IU5 = 0))]
3922#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3923pub unsafe fn Q6_R_round_RI_sat<const IU5: u32>(rs: i32) -> i32 {
3924    static_assert_uimm_bits!(IU5, 5);
3925    hexagon_A4_round_ri_sat(rs, IU5 as i32)
3926}
3927
3928/// `Rd32=round(Rs32,Rt32)`
3929///
3930/// Instruction Type: S_3op
3931/// Execution Slots: SLOT23
3932#[inline(always)]
3933#[cfg_attr(test, assert_instr(round))]
3934#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3935pub unsafe fn Q6_R_round_RR(rs: i32, rt: i32) -> i32 {
3936    hexagon_A4_round_rr(rs, rt)
3937}
3938
3939/// `Rd32=round(Rs32,Rt32):sat`
3940///
3941/// Instruction Type: S_3op
3942/// Execution Slots: SLOT23
3943#[inline(always)]
3944#[cfg_attr(test, assert_instr(round))]
3945#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3946pub unsafe fn Q6_R_round_RR_sat(rs: i32, rt: i32) -> i32 {
3947    hexagon_A4_round_rr_sat(rs, rt)
3948}
3949
3950/// `Pd4=tlbmatch(Rss32,Rt32)`
3951///
3952/// Instruction Type: ALU64
3953/// Execution Slots: SLOT23
3954#[inline(always)]
3955#[cfg_attr(test, assert_instr(tlbmatch))]
3956#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3957pub unsafe fn Q6_p_tlbmatch_PR(rss: i64, rt: i32) -> i32 {
3958    hexagon_A4_tlbmatch(rss, rt)
3959}
3960
3961/// `Pd4=any8(vcmpb.eq(Rss32,Rtt32))`
3962///
3963/// Instruction Type: ALU64
3964/// Execution Slots: SLOT23
3965#[inline(always)]
3966#[cfg_attr(test, assert_instr(any8))]
3967#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3968pub unsafe fn Q6_p_any8_vcmpb_eq_PP(rss: i64, rtt: i64) -> i32 {
3969    hexagon_A4_vcmpbeq_any(rss, rtt)
3970}
3971
3972/// `Pd4=vcmpb.eq(Rss32,#u8)`
3973///
3974/// Instruction Type: ALU64
3975/// Execution Slots: SLOT23
3976#[inline(always)]
3977#[rustc_legacy_const_generics(1)]
3978#[cfg_attr(test, assert_instr(vcmpb, IU8 = 0))]
3979#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3980pub unsafe fn Q6_p_vcmpb_eq_PI<const IU8: u32>(rss: i64) -> i32 {
3981    static_assert_uimm_bits!(IU8, 8);
3982    hexagon_A4_vcmpbeqi(rss, IU8 as i32)
3983}
3984
3985/// `Pd4=vcmpb.gt(Rss32,Rtt32)`
3986///
3987/// Instruction Type: ALU64
3988/// Execution Slots: SLOT23
3989#[inline(always)]
3990#[cfg_attr(test, assert_instr(vcmpb))]
3991#[unstable(feature = "stdarch_hexagon", issue = "151523")]
3992pub unsafe fn Q6_p_vcmpb_gt_PP(rss: i64, rtt: i64) -> i32 {
3993    hexagon_A4_vcmpbgt(rss, rtt)
3994}
3995
3996/// `Pd4=vcmpb.gt(Rss32,#s8)`
3997///
3998/// Instruction Type: ALU64
3999/// Execution Slots: SLOT23
4000#[inline(always)]
4001#[rustc_legacy_const_generics(1)]
4002#[cfg_attr(test, assert_instr(vcmpb, IS8 = 0))]
4003#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4004pub unsafe fn Q6_p_vcmpb_gt_PI<const IS8: i32>(rss: i64) -> i32 {
4005    static_assert_simm_bits!(IS8, 8);
4006    hexagon_A4_vcmpbgti(rss, IS8)
4007}
4008
4009/// `Pd4=vcmpb.gtu(Rss32,#u7)`
4010///
4011/// Instruction Type: ALU64
4012/// Execution Slots: SLOT23
4013#[inline(always)]
4014#[rustc_legacy_const_generics(1)]
4015#[cfg_attr(test, assert_instr(vcmpb, IU7 = 0))]
4016#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4017pub unsafe fn Q6_p_vcmpb_gtu_PI<const IU7: u32>(rss: i64) -> i32 {
4018    static_assert_uimm_bits!(IU7, 7);
4019    hexagon_A4_vcmpbgtui(rss, IU7 as i32)
4020}
4021
4022/// `Pd4=vcmph.eq(Rss32,#s8)`
4023///
4024/// Instruction Type: ALU64
4025/// Execution Slots: SLOT23
4026#[inline(always)]
4027#[rustc_legacy_const_generics(1)]
4028#[cfg_attr(test, assert_instr(vcmph, IS8 = 0))]
4029#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4030pub unsafe fn Q6_p_vcmph_eq_PI<const IS8: i32>(rss: i64) -> i32 {
4031    static_assert_simm_bits!(IS8, 8);
4032    hexagon_A4_vcmpheqi(rss, IS8)
4033}
4034
4035/// `Pd4=vcmph.gt(Rss32,#s8)`
4036///
4037/// Instruction Type: ALU64
4038/// Execution Slots: SLOT23
4039#[inline(always)]
4040#[rustc_legacy_const_generics(1)]
4041#[cfg_attr(test, assert_instr(vcmph, IS8 = 0))]
4042#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4043pub unsafe fn Q6_p_vcmph_gt_PI<const IS8: i32>(rss: i64) -> i32 {
4044    static_assert_simm_bits!(IS8, 8);
4045    hexagon_A4_vcmphgti(rss, IS8)
4046}
4047
4048/// `Pd4=vcmph.gtu(Rss32,#u7)`
4049///
4050/// Instruction Type: ALU64
4051/// Execution Slots: SLOT23
4052#[inline(always)]
4053#[rustc_legacy_const_generics(1)]
4054#[cfg_attr(test, assert_instr(vcmph, IU7 = 0))]
4055#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4056pub unsafe fn Q6_p_vcmph_gtu_PI<const IU7: u32>(rss: i64) -> i32 {
4057    static_assert_uimm_bits!(IU7, 7);
4058    hexagon_A4_vcmphgtui(rss, IU7 as i32)
4059}
4060
4061/// `Pd4=vcmpw.eq(Rss32,#s8)`
4062///
4063/// Instruction Type: ALU64
4064/// Execution Slots: SLOT23
4065#[inline(always)]
4066#[rustc_legacy_const_generics(1)]
4067#[cfg_attr(test, assert_instr(vcmpw, IS8 = 0))]
4068#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4069pub unsafe fn Q6_p_vcmpw_eq_PI<const IS8: i32>(rss: i64) -> i32 {
4070    static_assert_simm_bits!(IS8, 8);
4071    hexagon_A4_vcmpweqi(rss, IS8)
4072}
4073
4074/// `Pd4=vcmpw.gt(Rss32,#s8)`
4075///
4076/// Instruction Type: ALU64
4077/// Execution Slots: SLOT23
4078#[inline(always)]
4079#[rustc_legacy_const_generics(1)]
4080#[cfg_attr(test, assert_instr(vcmpw, IS8 = 0))]
4081#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4082pub unsafe fn Q6_p_vcmpw_gt_PI<const IS8: i32>(rss: i64) -> i32 {
4083    static_assert_simm_bits!(IS8, 8);
4084    hexagon_A4_vcmpwgti(rss, IS8)
4085}
4086
4087/// `Pd4=vcmpw.gtu(Rss32,#u7)`
4088///
4089/// Instruction Type: ALU64
4090/// Execution Slots: SLOT23
4091#[inline(always)]
4092#[rustc_legacy_const_generics(1)]
4093#[cfg_attr(test, assert_instr(vcmpw, IU7 = 0))]
4094#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4095pub unsafe fn Q6_p_vcmpw_gtu_PI<const IU7: u32>(rss: i64) -> i32 {
4096    static_assert_uimm_bits!(IU7, 7);
4097    hexagon_A4_vcmpwgtui(rss, IU7 as i32)
4098}
4099
4100/// `Rxx32=vrmaxh(Rss32,Ru32)`
4101///
4102/// Instruction Type: S_3op
4103/// Execution Slots: SLOT23
4104#[inline(always)]
4105#[cfg_attr(test, assert_instr(vrmaxh))]
4106#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4107pub unsafe fn Q6_P_vrmaxh_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
4108    hexagon_A4_vrmaxh(rxx, rss, ru)
4109}
4110
4111/// `Rxx32=vrmaxuh(Rss32,Ru32)`
4112///
4113/// Instruction Type: S_3op
4114/// Execution Slots: SLOT23
4115#[inline(always)]
4116#[cfg_attr(test, assert_instr(vrmaxuh))]
4117#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4118pub unsafe fn Q6_P_vrmaxuh_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
4119    hexagon_A4_vrmaxuh(rxx, rss, ru)
4120}
4121
4122/// `Rxx32=vrmaxuw(Rss32,Ru32)`
4123///
4124/// Instruction Type: S_3op
4125/// Execution Slots: SLOT23
4126#[inline(always)]
4127#[cfg_attr(test, assert_instr(vrmaxuw))]
4128#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4129pub unsafe fn Q6_P_vrmaxuw_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
4130    hexagon_A4_vrmaxuw(rxx, rss, ru)
4131}
4132
4133/// `Rxx32=vrmaxw(Rss32,Ru32)`
4134///
4135/// Instruction Type: S_3op
4136/// Execution Slots: SLOT23
4137#[inline(always)]
4138#[cfg_attr(test, assert_instr(vrmaxw))]
4139#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4140pub unsafe fn Q6_P_vrmaxw_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
4141    hexagon_A4_vrmaxw(rxx, rss, ru)
4142}
4143
4144/// `Rxx32=vrminh(Rss32,Ru32)`
4145///
4146/// Instruction Type: S_3op
4147/// Execution Slots: SLOT23
4148#[inline(always)]
4149#[cfg_attr(test, assert_instr(vrminh))]
4150#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4151pub unsafe fn Q6_P_vrminh_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
4152    hexagon_A4_vrminh(rxx, rss, ru)
4153}
4154
4155/// `Rxx32=vrminuh(Rss32,Ru32)`
4156///
4157/// Instruction Type: S_3op
4158/// Execution Slots: SLOT23
4159#[inline(always)]
4160#[cfg_attr(test, assert_instr(vrminuh))]
4161#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4162pub unsafe fn Q6_P_vrminuh_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
4163    hexagon_A4_vrminuh(rxx, rss, ru)
4164}
4165
4166/// `Rxx32=vrminuw(Rss32,Ru32)`
4167///
4168/// Instruction Type: S_3op
4169/// Execution Slots: SLOT23
4170#[inline(always)]
4171#[cfg_attr(test, assert_instr(vrminuw))]
4172#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4173pub unsafe fn Q6_P_vrminuw_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
4174    hexagon_A4_vrminuw(rxx, rss, ru)
4175}
4176
4177/// `Rxx32=vrminw(Rss32,Ru32)`
4178///
4179/// Instruction Type: S_3op
4180/// Execution Slots: SLOT23
4181#[inline(always)]
4182#[cfg_attr(test, assert_instr(vrminw))]
4183#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4184pub unsafe fn Q6_P_vrminw_PR(rxx: i64, rss: i64, ru: i32) -> i64 {
4185    hexagon_A4_vrminw(rxx, rss, ru)
4186}
4187
4188/// `Rd32=vaddhub(Rss32,Rtt32):sat`
4189///
4190/// Instruction Type: S_3op
4191/// Execution Slots: SLOT23
4192#[inline(always)]
4193#[cfg_attr(test, assert_instr(vaddhub))]
4194#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4195pub unsafe fn Q6_R_vaddhub_PP_sat(rss: i64, rtt: i64) -> i32 {
4196    hexagon_A5_vaddhubs(rss, rtt)
4197}
4198
4199/// `Pd4=all8(Ps4)`
4200///
4201/// Instruction Type: CR
4202/// Execution Slots: SLOT23
4203#[inline(always)]
4204#[cfg_attr(test, assert_instr(all8))]
4205#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4206pub unsafe fn Q6_p_all8_p(ps: i32) -> i32 {
4207    hexagon_C2_all8(ps)
4208}
4209
4210/// `Pd4=and(Pt4,Ps4)`
4211///
4212/// Instruction Type: CR
4213/// Execution Slots: SLOT23
4214#[inline(always)]
4215#[cfg_attr(test, assert_instr(and))]
4216#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4217pub unsafe fn Q6_p_and_pp(pt: i32, ps: i32) -> i32 {
4218    hexagon_C2_and(pt, ps)
4219}
4220
4221/// `Pd4=and(Pt4,!Ps4)`
4222///
4223/// Instruction Type: CR
4224/// Execution Slots: SLOT23
4225#[inline(always)]
4226#[cfg_attr(test, assert_instr(and))]
4227#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4228pub unsafe fn Q6_p_and_pnp(pt: i32, ps: i32) -> i32 {
4229    hexagon_C2_andn(pt, ps)
4230}
4231
4232/// `Pd4=any8(Ps4)`
4233///
4234/// Instruction Type: CR
4235/// Execution Slots: SLOT23
4236#[inline(always)]
4237#[cfg_attr(test, assert_instr(any8))]
4238#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4239pub unsafe fn Q6_p_any8_p(ps: i32) -> i32 {
4240    hexagon_C2_any8(ps)
4241}
4242
4243/// `Pd4=bitsclr(Rs32,Rt32)`
4244///
4245/// Instruction Type: S_3op
4246/// Execution Slots: SLOT23
4247#[inline(always)]
4248#[cfg_attr(test, assert_instr(bitsclr))]
4249#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4250pub unsafe fn Q6_p_bitsclr_RR(rs: i32, rt: i32) -> i32 {
4251    hexagon_C2_bitsclr(rs, rt)
4252}
4253
4254/// `Pd4=bitsclr(Rs32,#u6)`
4255///
4256/// Instruction Type: S_2op
4257/// Execution Slots: SLOT23
4258#[inline(always)]
4259#[rustc_legacy_const_generics(1)]
4260#[cfg_attr(test, assert_instr(bitsclr, IU6 = 0))]
4261#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4262pub unsafe fn Q6_p_bitsclr_RI<const IU6: u32>(rs: i32) -> i32 {
4263    static_assert_uimm_bits!(IU6, 6);
4264    hexagon_C2_bitsclri(rs, IU6 as i32)
4265}
4266
4267/// `Pd4=bitsset(Rs32,Rt32)`
4268///
4269/// Instruction Type: S_3op
4270/// Execution Slots: SLOT23
4271#[inline(always)]
4272#[cfg_attr(test, assert_instr(bitsset))]
4273#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4274pub unsafe fn Q6_p_bitsset_RR(rs: i32, rt: i32) -> i32 {
4275    hexagon_C2_bitsset(rs, rt)
4276}
4277
4278/// `Pd4=cmp.eq(Rs32,Rt32)`
4279///
4280/// Instruction Type: ALU32_3op
4281/// Execution Slots: SLOT0123
4282#[inline(always)]
4283#[cfg_attr(test, assert_instr(cmp))]
4284#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4285pub unsafe fn Q6_p_cmp_eq_RR(rs: i32, rt: i32) -> i32 {
4286    hexagon_C2_cmpeq(rs, rt)
4287}
4288
4289/// `Pd4=cmp.eq(Rs32,#s10)`
4290///
4291/// Instruction Type: ALU32_2op
4292/// Execution Slots: SLOT0123
4293#[inline(always)]
4294#[rustc_legacy_const_generics(1)]
4295#[cfg_attr(test, assert_instr(cmp, IS10 = 0))]
4296#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4297pub unsafe fn Q6_p_cmp_eq_RI<const IS10: i32>(rs: i32) -> i32 {
4298    static_assert_simm_bits!(IS10, 10);
4299    hexagon_C2_cmpeqi(rs, IS10)
4300}
4301
4302/// `Pd4=cmp.eq(Rss32,Rtt32)`
4303///
4304/// Instruction Type: ALU64
4305/// Execution Slots: SLOT23
4306#[inline(always)]
4307#[cfg_attr(test, assert_instr(cmp))]
4308#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4309pub unsafe fn Q6_p_cmp_eq_PP(rss: i64, rtt: i64) -> i32 {
4310    hexagon_C2_cmpeqp(rss, rtt)
4311}
4312
4313/// `Pd4=cmp.ge(Rs32,#s8)`
4314///
4315/// Instruction Type: ALU32_2op
4316/// Execution Slots: SLOT0123
4317#[inline(always)]
4318#[rustc_legacy_const_generics(1)]
4319#[cfg_attr(test, assert_instr(cmp, IS8 = 0))]
4320#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4321pub unsafe fn Q6_p_cmp_ge_RI<const IS8: i32>(rs: i32) -> i32 {
4322    static_assert_simm_bits!(IS8, 8);
4323    hexagon_C2_cmpgei(rs, IS8)
4324}
4325
4326/// `Pd4=cmp.geu(Rs32,#u8)`
4327///
4328/// Instruction Type: ALU32_2op
4329/// Execution Slots: SLOT0123
4330#[inline(always)]
4331#[rustc_legacy_const_generics(1)]
4332#[cfg_attr(test, assert_instr(cmp, IU8 = 0))]
4333#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4334pub unsafe fn Q6_p_cmp_geu_RI<const IU8: u32>(rs: i32) -> i32 {
4335    static_assert_uimm_bits!(IU8, 8);
4336    hexagon_C2_cmpgeui(rs, IU8 as i32)
4337}
4338
4339/// `Pd4=cmp.gt(Rs32,Rt32)`
4340///
4341/// Instruction Type: ALU32_3op
4342/// Execution Slots: SLOT0123
4343#[inline(always)]
4344#[cfg_attr(test, assert_instr(cmp))]
4345#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4346pub unsafe fn Q6_p_cmp_gt_RR(rs: i32, rt: i32) -> i32 {
4347    hexagon_C2_cmpgt(rs, rt)
4348}
4349
4350/// `Pd4=cmp.gt(Rs32,#s10)`
4351///
4352/// Instruction Type: ALU32_2op
4353/// Execution Slots: SLOT0123
4354#[inline(always)]
4355#[rustc_legacy_const_generics(1)]
4356#[cfg_attr(test, assert_instr(cmp, IS10 = 0))]
4357#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4358pub unsafe fn Q6_p_cmp_gt_RI<const IS10: i32>(rs: i32) -> i32 {
4359    static_assert_simm_bits!(IS10, 10);
4360    hexagon_C2_cmpgti(rs, IS10)
4361}
4362
4363/// `Pd4=cmp.gt(Rss32,Rtt32)`
4364///
4365/// Instruction Type: ALU64
4366/// Execution Slots: SLOT23
4367#[inline(always)]
4368#[cfg_attr(test, assert_instr(cmp))]
4369#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4370pub unsafe fn Q6_p_cmp_gt_PP(rss: i64, rtt: i64) -> i32 {
4371    hexagon_C2_cmpgtp(rss, rtt)
4372}
4373
4374/// `Pd4=cmp.gtu(Rs32,Rt32)`
4375///
4376/// Instruction Type: ALU32_3op
4377/// Execution Slots: SLOT0123
4378#[inline(always)]
4379#[cfg_attr(test, assert_instr(cmp))]
4380#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4381pub unsafe fn Q6_p_cmp_gtu_RR(rs: i32, rt: i32) -> i32 {
4382    hexagon_C2_cmpgtu(rs, rt)
4383}
4384
4385/// `Pd4=cmp.gtu(Rs32,#u9)`
4386///
4387/// Instruction Type: ALU32_2op
4388/// Execution Slots: SLOT0123
4389#[inline(always)]
4390#[rustc_legacy_const_generics(1)]
4391#[cfg_attr(test, assert_instr(cmp, IU9 = 0))]
4392#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4393pub unsafe fn Q6_p_cmp_gtu_RI<const IU9: u32>(rs: i32) -> i32 {
4394    static_assert_uimm_bits!(IU9, 9);
4395    hexagon_C2_cmpgtui(rs, IU9 as i32)
4396}
4397
4398/// `Pd4=cmp.gtu(Rss32,Rtt32)`
4399///
4400/// Instruction Type: ALU64
4401/// Execution Slots: SLOT23
4402#[inline(always)]
4403#[cfg_attr(test, assert_instr(cmp))]
4404#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4405pub unsafe fn Q6_p_cmp_gtu_PP(rss: i64, rtt: i64) -> i32 {
4406    hexagon_C2_cmpgtup(rss, rtt)
4407}
4408
4409/// `Pd4=cmp.lt(Rs32,Rt32)`
4410///
4411/// Instruction Type: ALU32_3op
4412/// Execution Slots: SLOT0123
4413#[inline(always)]
4414#[cfg_attr(test, assert_instr(cmp))]
4415#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4416pub unsafe fn Q6_p_cmp_lt_RR(rs: i32, rt: i32) -> i32 {
4417    hexagon_C2_cmplt(rs, rt)
4418}
4419
4420/// `Pd4=cmp.ltu(Rs32,Rt32)`
4421///
4422/// Instruction Type: ALU32_3op
4423/// Execution Slots: SLOT0123
4424#[inline(always)]
4425#[cfg_attr(test, assert_instr(cmp))]
4426#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4427pub unsafe fn Q6_p_cmp_ltu_RR(rs: i32, rt: i32) -> i32 {
4428    hexagon_C2_cmpltu(rs, rt)
4429}
4430
4431/// `Rdd32=mask(Pt4)`
4432///
4433/// Instruction Type: S_2op
4434/// Execution Slots: SLOT23
4435#[inline(always)]
4436#[cfg_attr(test, assert_instr(mask))]
4437#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4438pub unsafe fn Q6_P_mask_p(pt: i32) -> i64 {
4439    hexagon_C2_mask(pt)
4440}
4441
4442/// `Rd32=mux(Pu4,Rs32,Rt32)`
4443///
4444/// Instruction Type: ALU32_3op
4445/// Execution Slots: SLOT0123
4446#[inline(always)]
4447#[cfg_attr(test, assert_instr(mux))]
4448#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4449pub unsafe fn Q6_R_mux_pRR(pu: i32, rs: i32, rt: i32) -> i32 {
4450    hexagon_C2_mux(pu, rs, rt)
4451}
4452
4453/// `Rd32=mux(Pu4,#s8,#S8)`
4454///
4455/// Instruction Type: ALU32_2op
4456/// Execution Slots: SLOT0123
4457#[inline(always)]
4458#[rustc_legacy_const_generics(1, 2)]
4459#[cfg_attr(test, assert_instr(mux, IS8 = 0, IS8_2 = 0))]
4460#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4461pub unsafe fn Q6_R_mux_pII<const IS8: i32, const IS8_2: i32>(pu: i32) -> i32 {
4462    static_assert_simm_bits!(IS8, 8);
4463    static_assert_simm_bits!(IS8_2, 8);
4464    hexagon_C2_muxii(pu, IS8, IS8_2)
4465}
4466
4467/// `Rd32=mux(Pu4,Rs32,#s8)`
4468///
4469/// Instruction Type: ALU32_2op
4470/// Execution Slots: SLOT0123
4471#[inline(always)]
4472#[rustc_legacy_const_generics(2)]
4473#[cfg_attr(test, assert_instr(mux, IS8 = 0))]
4474#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4475pub unsafe fn Q6_R_mux_pRI<const IS8: i32>(pu: i32, rs: i32) -> i32 {
4476    static_assert_simm_bits!(IS8, 8);
4477    hexagon_C2_muxir(pu, rs, IS8)
4478}
4479
4480/// `Rd32=mux(Pu4,#s8,Rs32)`
4481///
4482/// Instruction Type: ALU32_2op
4483/// Execution Slots: SLOT0123
4484#[inline(always)]
4485#[rustc_legacy_const_generics(1)]
4486#[cfg_attr(test, assert_instr(mux, IS8 = 0))]
4487#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4488pub unsafe fn Q6_R_mux_pIR<const IS8: i32>(pu: i32, rs: i32) -> i32 {
4489    static_assert_simm_bits!(IS8, 8);
4490    hexagon_C2_muxri(pu, IS8, rs)
4491}
4492
4493/// `Pd4=not(Ps4)`
4494///
4495/// Instruction Type: CR
4496/// Execution Slots: SLOT23
4497#[inline(always)]
4498#[cfg_attr(test, assert_instr(not))]
4499#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4500pub unsafe fn Q6_p_not_p(ps: i32) -> i32 {
4501    hexagon_C2_not(ps)
4502}
4503
4504/// `Pd4=or(Pt4,Ps4)`
4505///
4506/// Instruction Type: CR
4507/// Execution Slots: SLOT23
4508#[inline(always)]
4509#[cfg_attr(test, assert_instr(or))]
4510#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4511pub unsafe fn Q6_p_or_pp(pt: i32, ps: i32) -> i32 {
4512    hexagon_C2_or(pt, ps)
4513}
4514
4515/// `Pd4=or(Pt4,!Ps4)`
4516///
4517/// Instruction Type: CR
4518/// Execution Slots: SLOT23
4519#[inline(always)]
4520#[cfg_attr(test, assert_instr(or))]
4521#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4522pub unsafe fn Q6_p_or_pnp(pt: i32, ps: i32) -> i32 {
4523    hexagon_C2_orn(pt, ps)
4524}
4525
4526/// `Pd4=Ps4`
4527///
4528/// Instruction Type: MAPPING
4529/// Execution Slots: SLOT0123
4530#[inline(always)]
4531#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4532pub unsafe fn Q6_p_equals_p(ps: i32) -> i32 {
4533    hexagon_C2_pxfer_map(ps)
4534}
4535
4536/// `Rd32=Ps4`
4537///
4538/// Instruction Type: S_2op
4539/// Execution Slots: SLOT23
4540#[inline(always)]
4541#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4542pub unsafe fn Q6_R_equals_p(ps: i32) -> i32 {
4543    hexagon_C2_tfrpr(ps)
4544}
4545
4546/// `Pd4=Rs32`
4547///
4548/// Instruction Type: S_2op
4549/// Execution Slots: SLOT23
4550#[inline(always)]
4551#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4552pub unsafe fn Q6_p_equals_R(rs: i32) -> i32 {
4553    hexagon_C2_tfrrp(rs)
4554}
4555
4556/// `Rd32=vitpack(Ps4,Pt4)`
4557///
4558/// Instruction Type: S_2op
4559/// Execution Slots: SLOT23
4560#[inline(always)]
4561#[cfg_attr(test, assert_instr(vitpack))]
4562#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4563pub unsafe fn Q6_R_vitpack_pp(ps: i32, pt: i32) -> i32 {
4564    hexagon_C2_vitpack(ps, pt)
4565}
4566
4567/// `Rdd32=vmux(Pu4,Rss32,Rtt32)`
4568///
4569/// Instruction Type: ALU64
4570/// Execution Slots: SLOT23
4571#[inline(always)]
4572#[cfg_attr(test, assert_instr(vmux))]
4573#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4574pub unsafe fn Q6_P_vmux_pPP(pu: i32, rss: i64, rtt: i64) -> i64 {
4575    hexagon_C2_vmux(pu, rss, rtt)
4576}
4577
4578/// `Pd4=xor(Ps4,Pt4)`
4579///
4580/// Instruction Type: CR
4581/// Execution Slots: SLOT23
4582#[inline(always)]
4583#[cfg_attr(test, assert_instr(xor))]
4584#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4585pub unsafe fn Q6_p_xor_pp(ps: i32, pt: i32) -> i32 {
4586    hexagon_C2_xor(ps, pt)
4587}
4588
4589/// `Pd4=and(Ps4,and(Pt4,Pu4))`
4590///
4591/// Instruction Type: CR
4592/// Execution Slots: SLOT23
4593#[inline(always)]
4594#[cfg_attr(test, assert_instr(and))]
4595#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4596pub unsafe fn Q6_p_and_and_ppp(ps: i32, pt: i32, pu: i32) -> i32 {
4597    hexagon_C4_and_and(ps, pt, pu)
4598}
4599
4600/// `Pd4=and(Ps4,and(Pt4,!Pu4))`
4601///
4602/// Instruction Type: CR
4603/// Execution Slots: SLOT23
4604#[inline(always)]
4605#[cfg_attr(test, assert_instr(and))]
4606#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4607pub unsafe fn Q6_p_and_and_ppnp(ps: i32, pt: i32, pu: i32) -> i32 {
4608    hexagon_C4_and_andn(ps, pt, pu)
4609}
4610
4611/// `Pd4=and(Ps4,or(Pt4,Pu4))`
4612///
4613/// Instruction Type: CR
4614/// Execution Slots: SLOT23
4615#[inline(always)]
4616#[cfg_attr(test, assert_instr(and))]
4617#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4618pub unsafe fn Q6_p_and_or_ppp(ps: i32, pt: i32, pu: i32) -> i32 {
4619    hexagon_C4_and_or(ps, pt, pu)
4620}
4621
4622/// `Pd4=and(Ps4,or(Pt4,!Pu4))`
4623///
4624/// Instruction Type: CR
4625/// Execution Slots: SLOT23
4626#[inline(always)]
4627#[cfg_attr(test, assert_instr(and))]
4628#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4629pub unsafe fn Q6_p_and_or_ppnp(ps: i32, pt: i32, pu: i32) -> i32 {
4630    hexagon_C4_and_orn(ps, pt, pu)
4631}
4632
4633/// `Pd4=!cmp.gt(Rs32,Rt32)`
4634///
4635/// Instruction Type: ALU32_3op
4636/// Execution Slots: SLOT0123
4637#[inline(always)]
4638#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4639pub unsafe fn Q6_p_not_cmp_gt_RR(rs: i32, rt: i32) -> i32 {
4640    hexagon_C4_cmplte(rs, rt)
4641}
4642
4643/// `Pd4=!cmp.gt(Rs32,#s10)`
4644///
4645/// Instruction Type: ALU32_2op
4646/// Execution Slots: SLOT0123
4647#[inline(always)]
4648#[rustc_legacy_const_generics(1)]
4649#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4650pub unsafe fn Q6_p_not_cmp_gt_RI<const IS10: i32>(rs: i32) -> i32 {
4651    static_assert_simm_bits!(IS10, 10);
4652    hexagon_C4_cmpltei(rs, IS10)
4653}
4654
4655/// `Pd4=!cmp.gtu(Rs32,Rt32)`
4656///
4657/// Instruction Type: ALU32_3op
4658/// Execution Slots: SLOT0123
4659#[inline(always)]
4660#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4661pub unsafe fn Q6_p_not_cmp_gtu_RR(rs: i32, rt: i32) -> i32 {
4662    hexagon_C4_cmplteu(rs, rt)
4663}
4664
4665/// `Pd4=!cmp.gtu(Rs32,#u9)`
4666///
4667/// Instruction Type: ALU32_2op
4668/// Execution Slots: SLOT0123
4669#[inline(always)]
4670#[rustc_legacy_const_generics(1)]
4671#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4672pub unsafe fn Q6_p_not_cmp_gtu_RI<const IU9: u32>(rs: i32) -> i32 {
4673    static_assert_uimm_bits!(IU9, 9);
4674    hexagon_C4_cmplteui(rs, IU9 as i32)
4675}
4676
4677/// `Pd4=!cmp.eq(Rs32,Rt32)`
4678///
4679/// Instruction Type: ALU32_3op
4680/// Execution Slots: SLOT0123
4681#[inline(always)]
4682#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4683pub unsafe fn Q6_p_not_cmp_eq_RR(rs: i32, rt: i32) -> i32 {
4684    hexagon_C4_cmpneq(rs, rt)
4685}
4686
4687/// `Pd4=!cmp.eq(Rs32,#s10)`
4688///
4689/// Instruction Type: ALU32_2op
4690/// Execution Slots: SLOT0123
4691#[inline(always)]
4692#[rustc_legacy_const_generics(1)]
4693#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4694pub unsafe fn Q6_p_not_cmp_eq_RI<const IS10: i32>(rs: i32) -> i32 {
4695    static_assert_simm_bits!(IS10, 10);
4696    hexagon_C4_cmpneqi(rs, IS10)
4697}
4698
4699/// `Pd4=fastcorner9(Ps4,Pt4)`
4700///
4701/// Instruction Type: CR
4702/// Execution Slots: SLOT23
4703#[inline(always)]
4704#[cfg_attr(test, assert_instr(fastcorner9))]
4705#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4706pub unsafe fn Q6_p_fastcorner9_pp(ps: i32, pt: i32) -> i32 {
4707    hexagon_C4_fastcorner9(ps, pt)
4708}
4709
4710/// `Pd4=!fastcorner9(Ps4,Pt4)`
4711///
4712/// Instruction Type: CR
4713/// Execution Slots: SLOT23
4714#[inline(always)]
4715#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4716pub unsafe fn Q6_p_not_fastcorner9_pp(ps: i32, pt: i32) -> i32 {
4717    hexagon_C4_fastcorner9_not(ps, pt)
4718}
4719
4720/// `Pd4=!bitsclr(Rs32,Rt32)`
4721///
4722/// Instruction Type: S_3op
4723/// Execution Slots: SLOT23
4724#[inline(always)]
4725#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4726pub unsafe fn Q6_p_not_bitsclr_RR(rs: i32, rt: i32) -> i32 {
4727    hexagon_C4_nbitsclr(rs, rt)
4728}
4729
4730/// `Pd4=!bitsclr(Rs32,#u6)`
4731///
4732/// Instruction Type: S_2op
4733/// Execution Slots: SLOT23
4734#[inline(always)]
4735#[rustc_legacy_const_generics(1)]
4736#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4737pub unsafe fn Q6_p_not_bitsclr_RI<const IU6: u32>(rs: i32) -> i32 {
4738    static_assert_uimm_bits!(IU6, 6);
4739    hexagon_C4_nbitsclri(rs, IU6 as i32)
4740}
4741
4742/// `Pd4=!bitsset(Rs32,Rt32)`
4743///
4744/// Instruction Type: S_3op
4745/// Execution Slots: SLOT23
4746#[inline(always)]
4747#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4748pub unsafe fn Q6_p_not_bitsset_RR(rs: i32, rt: i32) -> i32 {
4749    hexagon_C4_nbitsset(rs, rt)
4750}
4751
4752/// `Pd4=or(Ps4,and(Pt4,Pu4))`
4753///
4754/// Instruction Type: CR
4755/// Execution Slots: SLOT23
4756#[inline(always)]
4757#[cfg_attr(test, assert_instr(or))]
4758#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4759pub unsafe fn Q6_p_or_and_ppp(ps: i32, pt: i32, pu: i32) -> i32 {
4760    hexagon_C4_or_and(ps, pt, pu)
4761}
4762
4763/// `Pd4=or(Ps4,and(Pt4,!Pu4))`
4764///
4765/// Instruction Type: CR
4766/// Execution Slots: SLOT23
4767#[inline(always)]
4768#[cfg_attr(test, assert_instr(or))]
4769#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4770pub unsafe fn Q6_p_or_and_ppnp(ps: i32, pt: i32, pu: i32) -> i32 {
4771    hexagon_C4_or_andn(ps, pt, pu)
4772}
4773
4774/// `Pd4=or(Ps4,or(Pt4,Pu4))`
4775///
4776/// Instruction Type: CR
4777/// Execution Slots: SLOT23
4778#[inline(always)]
4779#[cfg_attr(test, assert_instr(or))]
4780#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4781pub unsafe fn Q6_p_or_or_ppp(ps: i32, pt: i32, pu: i32) -> i32 {
4782    hexagon_C4_or_or(ps, pt, pu)
4783}
4784
4785/// `Pd4=or(Ps4,or(Pt4,!Pu4))`
4786///
4787/// Instruction Type: CR
4788/// Execution Slots: SLOT23
4789#[inline(always)]
4790#[cfg_attr(test, assert_instr(or))]
4791#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4792pub unsafe fn Q6_p_or_or_ppnp(ps: i32, pt: i32, pu: i32) -> i32 {
4793    hexagon_C4_or_orn(ps, pt, pu)
4794}
4795
4796/// `Rdd32=convert_d2df(Rss32)`
4797///
4798/// Instruction Type: S_2op
4799/// Execution Slots: SLOT23
4800#[inline(always)]
4801#[cfg_attr(test, assert_instr(convert_d2df))]
4802#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4803pub unsafe fn Q6_P_convert_d2df_P(rss: i64) -> f64 {
4804    hexagon_F2_conv_d2df(rss)
4805}
4806
4807/// `Rd32=convert_d2sf(Rss32)`
4808///
4809/// Instruction Type: S_2op
4810/// Execution Slots: SLOT23
4811#[inline(always)]
4812#[cfg_attr(test, assert_instr(convert_d2sf))]
4813#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4814pub unsafe fn Q6_R_convert_d2sf_P(rss: i64) -> f32 {
4815    hexagon_F2_conv_d2sf(rss)
4816}
4817
4818/// `Rdd32=convert_df2d(Rss32)`
4819///
4820/// Instruction Type: S_2op
4821/// Execution Slots: SLOT23
4822#[inline(always)]
4823#[cfg_attr(test, assert_instr(convert_df2d))]
4824#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4825pub unsafe fn Q6_P_convert_df2d_P(rss: f64) -> i64 {
4826    hexagon_F2_conv_df2d(rss)
4827}
4828
4829/// `Rdd32=convert_df2d(Rss32):chop`
4830///
4831/// Instruction Type: S_2op
4832/// Execution Slots: SLOT23
4833#[inline(always)]
4834#[cfg_attr(test, assert_instr(convert_df2d))]
4835#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4836pub unsafe fn Q6_P_convert_df2d_P_chop(rss: f64) -> i64 {
4837    hexagon_F2_conv_df2d_chop(rss)
4838}
4839
4840/// `Rd32=convert_df2sf(Rss32)`
4841///
4842/// Instruction Type: S_2op
4843/// Execution Slots: SLOT23
4844#[inline(always)]
4845#[cfg_attr(test, assert_instr(convert_df2sf))]
4846#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4847pub unsafe fn Q6_R_convert_df2sf_P(rss: f64) -> f32 {
4848    hexagon_F2_conv_df2sf(rss)
4849}
4850
4851/// `Rdd32=convert_df2ud(Rss32)`
4852///
4853/// Instruction Type: S_2op
4854/// Execution Slots: SLOT23
4855#[inline(always)]
4856#[cfg_attr(test, assert_instr(convert_df2ud))]
4857#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4858pub unsafe fn Q6_P_convert_df2ud_P(rss: f64) -> i64 {
4859    hexagon_F2_conv_df2ud(rss)
4860}
4861
4862/// `Rdd32=convert_df2ud(Rss32):chop`
4863///
4864/// Instruction Type: S_2op
4865/// Execution Slots: SLOT23
4866#[inline(always)]
4867#[cfg_attr(test, assert_instr(convert_df2ud))]
4868#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4869pub unsafe fn Q6_P_convert_df2ud_P_chop(rss: f64) -> i64 {
4870    hexagon_F2_conv_df2ud_chop(rss)
4871}
4872
4873/// `Rd32=convert_df2uw(Rss32)`
4874///
4875/// Instruction Type: S_2op
4876/// Execution Slots: SLOT23
4877#[inline(always)]
4878#[cfg_attr(test, assert_instr(convert_df2uw))]
4879#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4880pub unsafe fn Q6_R_convert_df2uw_P(rss: f64) -> i32 {
4881    hexagon_F2_conv_df2uw(rss)
4882}
4883
4884/// `Rd32=convert_df2uw(Rss32):chop`
4885///
4886/// Instruction Type: S_2op
4887/// Execution Slots: SLOT23
4888#[inline(always)]
4889#[cfg_attr(test, assert_instr(convert_df2uw))]
4890#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4891pub unsafe fn Q6_R_convert_df2uw_P_chop(rss: f64) -> i32 {
4892    hexagon_F2_conv_df2uw_chop(rss)
4893}
4894
4895/// `Rd32=convert_df2w(Rss32)`
4896///
4897/// Instruction Type: S_2op
4898/// Execution Slots: SLOT23
4899#[inline(always)]
4900#[cfg_attr(test, assert_instr(convert_df2w))]
4901#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4902pub unsafe fn Q6_R_convert_df2w_P(rss: f64) -> i32 {
4903    hexagon_F2_conv_df2w(rss)
4904}
4905
4906/// `Rd32=convert_df2w(Rss32):chop`
4907///
4908/// Instruction Type: S_2op
4909/// Execution Slots: SLOT23
4910#[inline(always)]
4911#[cfg_attr(test, assert_instr(convert_df2w))]
4912#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4913pub unsafe fn Q6_R_convert_df2w_P_chop(rss: f64) -> i32 {
4914    hexagon_F2_conv_df2w_chop(rss)
4915}
4916
4917/// `Rdd32=convert_sf2d(Rs32)`
4918///
4919/// Instruction Type: S_2op
4920/// Execution Slots: SLOT23
4921#[inline(always)]
4922#[cfg_attr(test, assert_instr(convert_sf2d))]
4923#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4924pub unsafe fn Q6_P_convert_sf2d_R(rs: f32) -> i64 {
4925    hexagon_F2_conv_sf2d(rs)
4926}
4927
4928/// `Rdd32=convert_sf2d(Rs32):chop`
4929///
4930/// Instruction Type: S_2op
4931/// Execution Slots: SLOT23
4932#[inline(always)]
4933#[cfg_attr(test, assert_instr(convert_sf2d))]
4934#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4935pub unsafe fn Q6_P_convert_sf2d_R_chop(rs: f32) -> i64 {
4936    hexagon_F2_conv_sf2d_chop(rs)
4937}
4938
4939/// `Rdd32=convert_sf2df(Rs32)`
4940///
4941/// Instruction Type: S_2op
4942/// Execution Slots: SLOT23
4943#[inline(always)]
4944#[cfg_attr(test, assert_instr(convert_sf2df))]
4945#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4946pub unsafe fn Q6_P_convert_sf2df_R(rs: f32) -> f64 {
4947    hexagon_F2_conv_sf2df(rs)
4948}
4949
4950/// `Rdd32=convert_sf2ud(Rs32)`
4951///
4952/// Instruction Type: S_2op
4953/// Execution Slots: SLOT23
4954#[inline(always)]
4955#[cfg_attr(test, assert_instr(convert_sf2ud))]
4956#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4957pub unsafe fn Q6_P_convert_sf2ud_R(rs: f32) -> i64 {
4958    hexagon_F2_conv_sf2ud(rs)
4959}
4960
4961/// `Rdd32=convert_sf2ud(Rs32):chop`
4962///
4963/// Instruction Type: S_2op
4964/// Execution Slots: SLOT23
4965#[inline(always)]
4966#[cfg_attr(test, assert_instr(convert_sf2ud))]
4967#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4968pub unsafe fn Q6_P_convert_sf2ud_R_chop(rs: f32) -> i64 {
4969    hexagon_F2_conv_sf2ud_chop(rs)
4970}
4971
4972/// `Rd32=convert_sf2uw(Rs32)`
4973///
4974/// Instruction Type: S_2op
4975/// Execution Slots: SLOT23
4976#[inline(always)]
4977#[cfg_attr(test, assert_instr(convert_sf2uw))]
4978#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4979pub unsafe fn Q6_R_convert_sf2uw_R(rs: f32) -> i32 {
4980    hexagon_F2_conv_sf2uw(rs)
4981}
4982
4983/// `Rd32=convert_sf2uw(Rs32):chop`
4984///
4985/// Instruction Type: S_2op
4986/// Execution Slots: SLOT23
4987#[inline(always)]
4988#[cfg_attr(test, assert_instr(convert_sf2uw))]
4989#[unstable(feature = "stdarch_hexagon", issue = "151523")]
4990pub unsafe fn Q6_R_convert_sf2uw_R_chop(rs: f32) -> i32 {
4991    hexagon_F2_conv_sf2uw_chop(rs)
4992}
4993
4994/// `Rd32=convert_sf2w(Rs32)`
4995///
4996/// Instruction Type: S_2op
4997/// Execution Slots: SLOT23
4998#[inline(always)]
4999#[cfg_attr(test, assert_instr(convert_sf2w))]
5000#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5001pub unsafe fn Q6_R_convert_sf2w_R(rs: f32) -> i32 {
5002    hexagon_F2_conv_sf2w(rs)
5003}
5004
5005/// `Rd32=convert_sf2w(Rs32):chop`
5006///
5007/// Instruction Type: S_2op
5008/// Execution Slots: SLOT23
5009#[inline(always)]
5010#[cfg_attr(test, assert_instr(convert_sf2w))]
5011#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5012pub unsafe fn Q6_R_convert_sf2w_R_chop(rs: f32) -> i32 {
5013    hexagon_F2_conv_sf2w_chop(rs)
5014}
5015
5016/// `Rdd32=convert_ud2df(Rss32)`
5017///
5018/// Instruction Type: S_2op
5019/// Execution Slots: SLOT23
5020#[inline(always)]
5021#[cfg_attr(test, assert_instr(convert_ud2df))]
5022#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5023pub unsafe fn Q6_P_convert_ud2df_P(rss: i64) -> f64 {
5024    hexagon_F2_conv_ud2df(rss)
5025}
5026
5027/// `Rd32=convert_ud2sf(Rss32)`
5028///
5029/// Instruction Type: S_2op
5030/// Execution Slots: SLOT23
5031#[inline(always)]
5032#[cfg_attr(test, assert_instr(convert_ud2sf))]
5033#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5034pub unsafe fn Q6_R_convert_ud2sf_P(rss: i64) -> f32 {
5035    hexagon_F2_conv_ud2sf(rss)
5036}
5037
5038/// `Rdd32=convert_uw2df(Rs32)`
5039///
5040/// Instruction Type: S_2op
5041/// Execution Slots: SLOT23
5042#[inline(always)]
5043#[cfg_attr(test, assert_instr(convert_uw2df))]
5044#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5045pub unsafe fn Q6_P_convert_uw2df_R(rs: i32) -> f64 {
5046    hexagon_F2_conv_uw2df(rs)
5047}
5048
5049/// `Rd32=convert_uw2sf(Rs32)`
5050///
5051/// Instruction Type: S_2op
5052/// Execution Slots: SLOT23
5053#[inline(always)]
5054#[cfg_attr(test, assert_instr(convert_uw2sf))]
5055#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5056pub unsafe fn Q6_R_convert_uw2sf_R(rs: i32) -> f32 {
5057    hexagon_F2_conv_uw2sf(rs)
5058}
5059
5060/// `Rdd32=convert_w2df(Rs32)`
5061///
5062/// Instruction Type: S_2op
5063/// Execution Slots: SLOT23
5064#[inline(always)]
5065#[cfg_attr(test, assert_instr(convert_w2df))]
5066#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5067pub unsafe fn Q6_P_convert_w2df_R(rs: i32) -> f64 {
5068    hexagon_F2_conv_w2df(rs)
5069}
5070
5071/// `Rd32=convert_w2sf(Rs32)`
5072///
5073/// Instruction Type: S_2op
5074/// Execution Slots: SLOT23
5075#[inline(always)]
5076#[cfg_attr(test, assert_instr(convert_w2sf))]
5077#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5078pub unsafe fn Q6_R_convert_w2sf_R(rs: i32) -> f32 {
5079    hexagon_F2_conv_w2sf(rs)
5080}
5081
5082/// `Pd4=dfclass(Rss32,#u5)`
5083///
5084/// Instruction Type: ALU64
5085/// Execution Slots: SLOT23
5086#[inline(always)]
5087#[rustc_legacy_const_generics(1)]
5088#[cfg_attr(test, assert_instr(dfclass, IU5 = 0))]
5089#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5090pub unsafe fn Q6_p_dfclass_PI<const IU5: u32>(rss: f64) -> i32 {
5091    static_assert_uimm_bits!(IU5, 5);
5092    hexagon_F2_dfclass(rss, IU5 as i32)
5093}
5094
5095/// `Pd4=dfcmp.eq(Rss32,Rtt32)`
5096///
5097/// Instruction Type: ALU64
5098/// Execution Slots: SLOT23
5099#[inline(always)]
5100#[cfg_attr(test, assert_instr(dfcmp))]
5101#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5102pub unsafe fn Q6_p_dfcmp_eq_PP(rss: f64, rtt: f64) -> i32 {
5103    hexagon_F2_dfcmpeq(rss, rtt)
5104}
5105
5106/// `Pd4=dfcmp.ge(Rss32,Rtt32)`
5107///
5108/// Instruction Type: ALU64
5109/// Execution Slots: SLOT23
5110#[inline(always)]
5111#[cfg_attr(test, assert_instr(dfcmp))]
5112#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5113pub unsafe fn Q6_p_dfcmp_ge_PP(rss: f64, rtt: f64) -> i32 {
5114    hexagon_F2_dfcmpge(rss, rtt)
5115}
5116
5117/// `Pd4=dfcmp.gt(Rss32,Rtt32)`
5118///
5119/// Instruction Type: ALU64
5120/// Execution Slots: SLOT23
5121#[inline(always)]
5122#[cfg_attr(test, assert_instr(dfcmp))]
5123#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5124pub unsafe fn Q6_p_dfcmp_gt_PP(rss: f64, rtt: f64) -> i32 {
5125    hexagon_F2_dfcmpgt(rss, rtt)
5126}
5127
5128/// `Pd4=dfcmp.uo(Rss32,Rtt32)`
5129///
5130/// Instruction Type: ALU64
5131/// Execution Slots: SLOT23
5132#[inline(always)]
5133#[cfg_attr(test, assert_instr(dfcmp))]
5134#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5135pub unsafe fn Q6_p_dfcmp_uo_PP(rss: f64, rtt: f64) -> i32 {
5136    hexagon_F2_dfcmpuo(rss, rtt)
5137}
5138
5139/// `Rdd32=dfmake(#u10):neg`
5140///
5141/// Instruction Type: ALU64
5142/// Execution Slots: SLOT23
5143#[inline(always)]
5144#[rustc_legacy_const_generics(0)]
5145#[cfg_attr(test, assert_instr(dfmake, IU10 = 0))]
5146#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5147pub unsafe fn Q6_P_dfmake_I_neg<const IU10: u32>() -> f64 {
5148    static_assert_uimm_bits!(IU10, 10);
5149    hexagon_F2_dfimm_n(IU10 as i32)
5150}
5151
5152/// `Rdd32=dfmake(#u10):pos`
5153///
5154/// Instruction Type: ALU64
5155/// Execution Slots: SLOT23
5156#[inline(always)]
5157#[rustc_legacy_const_generics(0)]
5158#[cfg_attr(test, assert_instr(dfmake, IU10 = 0))]
5159#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5160pub unsafe fn Q6_P_dfmake_I_pos<const IU10: u32>() -> f64 {
5161    static_assert_uimm_bits!(IU10, 10);
5162    hexagon_F2_dfimm_p(IU10 as i32)
5163}
5164
5165/// `Rd32=sfadd(Rs32,Rt32)`
5166///
5167/// Instruction Type: M
5168/// Execution Slots: SLOT23
5169#[inline(always)]
5170#[cfg_attr(test, assert_instr(sfadd))]
5171#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5172pub unsafe fn Q6_R_sfadd_RR(rs: f32, rt: f32) -> f32 {
5173    hexagon_F2_sfadd(rs, rt)
5174}
5175
5176/// `Pd4=sfclass(Rs32,#u5)`
5177///
5178/// Instruction Type: S_2op
5179/// Execution Slots: SLOT23
5180#[inline(always)]
5181#[rustc_legacy_const_generics(1)]
5182#[cfg_attr(test, assert_instr(sfclass, IU5 = 0))]
5183#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5184pub unsafe fn Q6_p_sfclass_RI<const IU5: u32>(rs: f32) -> i32 {
5185    static_assert_uimm_bits!(IU5, 5);
5186    hexagon_F2_sfclass(rs, IU5 as i32)
5187}
5188
5189/// `Pd4=sfcmp.eq(Rs32,Rt32)`
5190///
5191/// Instruction Type: S_3op
5192/// Execution Slots: SLOT23
5193#[inline(always)]
5194#[cfg_attr(test, assert_instr(sfcmp))]
5195#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5196pub unsafe fn Q6_p_sfcmp_eq_RR(rs: f32, rt: f32) -> i32 {
5197    hexagon_F2_sfcmpeq(rs, rt)
5198}
5199
5200/// `Pd4=sfcmp.ge(Rs32,Rt32)`
5201///
5202/// Instruction Type: S_3op
5203/// Execution Slots: SLOT23
5204#[inline(always)]
5205#[cfg_attr(test, assert_instr(sfcmp))]
5206#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5207pub unsafe fn Q6_p_sfcmp_ge_RR(rs: f32, rt: f32) -> i32 {
5208    hexagon_F2_sfcmpge(rs, rt)
5209}
5210
5211/// `Pd4=sfcmp.gt(Rs32,Rt32)`
5212///
5213/// Instruction Type: S_3op
5214/// Execution Slots: SLOT23
5215#[inline(always)]
5216#[cfg_attr(test, assert_instr(sfcmp))]
5217#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5218pub unsafe fn Q6_p_sfcmp_gt_RR(rs: f32, rt: f32) -> i32 {
5219    hexagon_F2_sfcmpgt(rs, rt)
5220}
5221
5222/// `Pd4=sfcmp.uo(Rs32,Rt32)`
5223///
5224/// Instruction Type: S_3op
5225/// Execution Slots: SLOT23
5226#[inline(always)]
5227#[cfg_attr(test, assert_instr(sfcmp))]
5228#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5229pub unsafe fn Q6_p_sfcmp_uo_RR(rs: f32, rt: f32) -> i32 {
5230    hexagon_F2_sfcmpuo(rs, rt)
5231}
5232
5233/// `Rd32=sffixupd(Rs32,Rt32)`
5234///
5235/// Instruction Type: M
5236/// Execution Slots: SLOT23
5237#[inline(always)]
5238#[cfg_attr(test, assert_instr(sffixupd))]
5239#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5240pub unsafe fn Q6_R_sffixupd_RR(rs: f32, rt: f32) -> f32 {
5241    hexagon_F2_sffixupd(rs, rt)
5242}
5243
5244/// `Rd32=sffixupn(Rs32,Rt32)`
5245///
5246/// Instruction Type: M
5247/// Execution Slots: SLOT23
5248#[inline(always)]
5249#[cfg_attr(test, assert_instr(sffixupn))]
5250#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5251pub unsafe fn Q6_R_sffixupn_RR(rs: f32, rt: f32) -> f32 {
5252    hexagon_F2_sffixupn(rs, rt)
5253}
5254
5255/// `Rd32=sffixupr(Rs32)`
5256///
5257/// Instruction Type: S_2op
5258/// Execution Slots: SLOT23
5259#[inline(always)]
5260#[cfg_attr(test, assert_instr(sffixupr))]
5261#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5262pub unsafe fn Q6_R_sffixupr_R(rs: f32) -> f32 {
5263    hexagon_F2_sffixupr(rs)
5264}
5265
5266/// `Rx32+=sfmpy(Rs32,Rt32)`
5267///
5268/// Instruction Type: M
5269/// Execution Slots: SLOT23
5270#[inline(always)]
5271#[cfg_attr(test, assert_instr(sfmpy))]
5272#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5273pub unsafe fn Q6_R_sfmpyacc_RR(rx: f32, rs: f32, rt: f32) -> f32 {
5274    hexagon_F2_sffma(rx, rs, rt)
5275}
5276
5277/// `Rx32+=sfmpy(Rs32,Rt32):lib`
5278///
5279/// Instruction Type: M
5280/// Execution Slots: SLOT23
5281#[inline(always)]
5282#[cfg_attr(test, assert_instr(sfmpy))]
5283#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5284pub unsafe fn Q6_R_sfmpyacc_RR_lib(rx: f32, rs: f32, rt: f32) -> f32 {
5285    hexagon_F2_sffma_lib(rx, rs, rt)
5286}
5287
5288/// `Rx32+=sfmpy(Rs32,Rt32,Pu4):scale`
5289///
5290/// Instruction Type: M
5291/// Execution Slots: SLOT23
5292#[inline(always)]
5293#[cfg_attr(test, assert_instr(sfmpy))]
5294#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5295pub unsafe fn Q6_R_sfmpyacc_RRp_scale(rx: f32, rs: f32, rt: f32, pu: i32) -> f32 {
5296    hexagon_F2_sffma_sc(rx, rs, rt, pu)
5297}
5298
5299/// `Rx32-=sfmpy(Rs32,Rt32)`
5300///
5301/// Instruction Type: M
5302/// Execution Slots: SLOT23
5303#[inline(always)]
5304#[cfg_attr(test, assert_instr(sfmpy))]
5305#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5306pub unsafe fn Q6_R_sfmpynac_RR(rx: f32, rs: f32, rt: f32) -> f32 {
5307    hexagon_F2_sffms(rx, rs, rt)
5308}
5309
5310/// `Rx32-=sfmpy(Rs32,Rt32):lib`
5311///
5312/// Instruction Type: M
5313/// Execution Slots: SLOT23
5314#[inline(always)]
5315#[cfg_attr(test, assert_instr(sfmpy))]
5316#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5317pub unsafe fn Q6_R_sfmpynac_RR_lib(rx: f32, rs: f32, rt: f32) -> f32 {
5318    hexagon_F2_sffms_lib(rx, rs, rt)
5319}
5320
5321/// `Rd32=sfmake(#u10):neg`
5322///
5323/// Instruction Type: ALU64
5324/// Execution Slots: SLOT23
5325#[inline(always)]
5326#[rustc_legacy_const_generics(0)]
5327#[cfg_attr(test, assert_instr(sfmake, IU10 = 0))]
5328#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5329pub unsafe fn Q6_R_sfmake_I_neg<const IU10: u32>() -> f32 {
5330    static_assert_uimm_bits!(IU10, 10);
5331    hexagon_F2_sfimm_n(IU10 as i32)
5332}
5333
5334/// `Rd32=sfmake(#u10):pos`
5335///
5336/// Instruction Type: ALU64
5337/// Execution Slots: SLOT23
5338#[inline(always)]
5339#[rustc_legacy_const_generics(0)]
5340#[cfg_attr(test, assert_instr(sfmake, IU10 = 0))]
5341#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5342pub unsafe fn Q6_R_sfmake_I_pos<const IU10: u32>() -> f32 {
5343    static_assert_uimm_bits!(IU10, 10);
5344    hexagon_F2_sfimm_p(IU10 as i32)
5345}
5346
5347/// `Rd32=sfmax(Rs32,Rt32)`
5348///
5349/// Instruction Type: M
5350/// Execution Slots: SLOT23
5351#[inline(always)]
5352#[cfg_attr(test, assert_instr(sfmax))]
5353#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5354pub unsafe fn Q6_R_sfmax_RR(rs: f32, rt: f32) -> f32 {
5355    hexagon_F2_sfmax(rs, rt)
5356}
5357
5358/// `Rd32=sfmin(Rs32,Rt32)`
5359///
5360/// Instruction Type: M
5361/// Execution Slots: SLOT23
5362#[inline(always)]
5363#[cfg_attr(test, assert_instr(sfmin))]
5364#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5365pub unsafe fn Q6_R_sfmin_RR(rs: f32, rt: f32) -> f32 {
5366    hexagon_F2_sfmin(rs, rt)
5367}
5368
5369/// `Rd32=sfmpy(Rs32,Rt32)`
5370///
5371/// Instruction Type: M
5372/// Execution Slots: SLOT23
5373#[inline(always)]
5374#[cfg_attr(test, assert_instr(sfmpy))]
5375#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5376pub unsafe fn Q6_R_sfmpy_RR(rs: f32, rt: f32) -> f32 {
5377    hexagon_F2_sfmpy(rs, rt)
5378}
5379
5380/// `Rd32=sfsub(Rs32,Rt32)`
5381///
5382/// Instruction Type: M
5383/// Execution Slots: SLOT23
5384#[inline(always)]
5385#[cfg_attr(test, assert_instr(sfsub))]
5386#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5387pub unsafe fn Q6_R_sfsub_RR(rs: f32, rt: f32) -> f32 {
5388    hexagon_F2_sfsub(rs, rt)
5389}
5390
5391/// `Rx32+=add(Rs32,Rt32)`
5392///
5393/// Instruction Type: M
5394/// Execution Slots: SLOT23
5395#[inline(always)]
5396#[cfg_attr(test, assert_instr(add))]
5397#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5398pub unsafe fn Q6_R_addacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
5399    hexagon_M2_acci(rx, rs, rt)
5400}
5401
5402/// `Rx32+=add(Rs32,#s8)`
5403///
5404/// Instruction Type: M
5405/// Execution Slots: SLOT23
5406#[inline(always)]
5407#[rustc_legacy_const_generics(2)]
5408#[cfg_attr(test, assert_instr(add, IS8 = 0))]
5409#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5410pub unsafe fn Q6_R_addacc_RI<const IS8: i32>(rx: i32, rs: i32) -> i32 {
5411    static_assert_simm_bits!(IS8, 8);
5412    hexagon_M2_accii(rx, rs, IS8)
5413}
5414
5415/// `Rxx32+=cmpyi(Rs32,Rt32)`
5416///
5417/// Instruction Type: M
5418/// Execution Slots: SLOT23
5419#[inline(always)]
5420#[cfg_attr(test, assert_instr(cmpyi))]
5421#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5422pub unsafe fn Q6_P_cmpyiacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
5423    hexagon_M2_cmaci_s0(rxx, rs, rt)
5424}
5425
5426/// `Rxx32+=cmpyr(Rs32,Rt32)`
5427///
5428/// Instruction Type: M
5429/// Execution Slots: SLOT23
5430#[inline(always)]
5431#[cfg_attr(test, assert_instr(cmpyr))]
5432#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5433pub unsafe fn Q6_P_cmpyracc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
5434    hexagon_M2_cmacr_s0(rxx, rs, rt)
5435}
5436
5437/// `Rxx32+=cmpy(Rs32,Rt32):sat`
5438///
5439/// Instruction Type: M
5440/// Execution Slots: SLOT23
5441#[inline(always)]
5442#[cfg_attr(test, assert_instr(cmpy))]
5443#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5444pub unsafe fn Q6_P_cmpyacc_RR_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
5445    hexagon_M2_cmacs_s0(rxx, rs, rt)
5446}
5447
5448/// `Rxx32+=cmpy(Rs32,Rt32):<<1:sat`
5449///
5450/// Instruction Type: M
5451/// Execution Slots: SLOT23
5452#[inline(always)]
5453#[cfg_attr(test, assert_instr(cmpy))]
5454#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5455pub unsafe fn Q6_P_cmpyacc_RR_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
5456    hexagon_M2_cmacs_s1(rxx, rs, rt)
5457}
5458
5459/// `Rxx32+=cmpy(Rs32,Rt32*):sat`
5460///
5461/// Instruction Type: M
5462/// Execution Slots: SLOT23
5463#[inline(always)]
5464#[cfg_attr(test, assert_instr(cmpy))]
5465#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5466pub unsafe fn Q6_P_cmpyacc_RR_conj_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
5467    hexagon_M2_cmacsc_s0(rxx, rs, rt)
5468}
5469
5470/// `Rxx32+=cmpy(Rs32,Rt32*):<<1:sat`
5471///
5472/// Instruction Type: M
5473/// Execution Slots: SLOT23
5474#[inline(always)]
5475#[cfg_attr(test, assert_instr(cmpy))]
5476#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5477pub unsafe fn Q6_P_cmpyacc_RR_conj_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
5478    hexagon_M2_cmacsc_s1(rxx, rs, rt)
5479}
5480
5481/// `Rdd32=cmpyi(Rs32,Rt32)`
5482///
5483/// Instruction Type: M
5484/// Execution Slots: SLOT23
5485#[inline(always)]
5486#[cfg_attr(test, assert_instr(cmpyi))]
5487#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5488pub unsafe fn Q6_P_cmpyi_RR(rs: i32, rt: i32) -> i64 {
5489    hexagon_M2_cmpyi_s0(rs, rt)
5490}
5491
5492/// `Rdd32=cmpyr(Rs32,Rt32)`
5493///
5494/// Instruction Type: M
5495/// Execution Slots: SLOT23
5496#[inline(always)]
5497#[cfg_attr(test, assert_instr(cmpyr))]
5498#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5499pub unsafe fn Q6_P_cmpyr_RR(rs: i32, rt: i32) -> i64 {
5500    hexagon_M2_cmpyr_s0(rs, rt)
5501}
5502
5503/// `Rd32=cmpy(Rs32,Rt32):rnd:sat`
5504///
5505/// Instruction Type: M
5506/// Execution Slots: SLOT23
5507#[inline(always)]
5508#[cfg_attr(test, assert_instr(cmpy))]
5509#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5510pub unsafe fn Q6_R_cmpy_RR_rnd_sat(rs: i32, rt: i32) -> i32 {
5511    hexagon_M2_cmpyrs_s0(rs, rt)
5512}
5513
5514/// `Rd32=cmpy(Rs32,Rt32):<<1:rnd:sat`
5515///
5516/// Instruction Type: M
5517/// Execution Slots: SLOT23
5518#[inline(always)]
5519#[cfg_attr(test, assert_instr(cmpy))]
5520#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5521pub unsafe fn Q6_R_cmpy_RR_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
5522    hexagon_M2_cmpyrs_s1(rs, rt)
5523}
5524
5525/// `Rd32=cmpy(Rs32,Rt32*):rnd:sat`
5526///
5527/// Instruction Type: M
5528/// Execution Slots: SLOT23
5529#[inline(always)]
5530#[cfg_attr(test, assert_instr(cmpy))]
5531#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5532pub unsafe fn Q6_R_cmpy_RR_conj_rnd_sat(rs: i32, rt: i32) -> i32 {
5533    hexagon_M2_cmpyrsc_s0(rs, rt)
5534}
5535
5536/// `Rd32=cmpy(Rs32,Rt32*):<<1:rnd:sat`
5537///
5538/// Instruction Type: M
5539/// Execution Slots: SLOT23
5540#[inline(always)]
5541#[cfg_attr(test, assert_instr(cmpy))]
5542#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5543pub unsafe fn Q6_R_cmpy_RR_conj_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
5544    hexagon_M2_cmpyrsc_s1(rs, rt)
5545}
5546
5547/// `Rdd32=cmpy(Rs32,Rt32):sat`
5548///
5549/// Instruction Type: M
5550/// Execution Slots: SLOT23
5551#[inline(always)]
5552#[cfg_attr(test, assert_instr(cmpy))]
5553#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5554pub unsafe fn Q6_P_cmpy_RR_sat(rs: i32, rt: i32) -> i64 {
5555    hexagon_M2_cmpys_s0(rs, rt)
5556}
5557
5558/// `Rdd32=cmpy(Rs32,Rt32):<<1:sat`
5559///
5560/// Instruction Type: M
5561/// Execution Slots: SLOT23
5562#[inline(always)]
5563#[cfg_attr(test, assert_instr(cmpy))]
5564#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5565pub unsafe fn Q6_P_cmpy_RR_s1_sat(rs: i32, rt: i32) -> i64 {
5566    hexagon_M2_cmpys_s1(rs, rt)
5567}
5568
5569/// `Rdd32=cmpy(Rs32,Rt32*):sat`
5570///
5571/// Instruction Type: M
5572/// Execution Slots: SLOT23
5573#[inline(always)]
5574#[cfg_attr(test, assert_instr(cmpy))]
5575#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5576pub unsafe fn Q6_P_cmpy_RR_conj_sat(rs: i32, rt: i32) -> i64 {
5577    hexagon_M2_cmpysc_s0(rs, rt)
5578}
5579
5580/// `Rdd32=cmpy(Rs32,Rt32*):<<1:sat`
5581///
5582/// Instruction Type: M
5583/// Execution Slots: SLOT23
5584#[inline(always)]
5585#[cfg_attr(test, assert_instr(cmpy))]
5586#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5587pub unsafe fn Q6_P_cmpy_RR_conj_s1_sat(rs: i32, rt: i32) -> i64 {
5588    hexagon_M2_cmpysc_s1(rs, rt)
5589}
5590
5591/// `Rxx32-=cmpy(Rs32,Rt32):sat`
5592///
5593/// Instruction Type: M
5594/// Execution Slots: SLOT23
5595#[inline(always)]
5596#[cfg_attr(test, assert_instr(cmpy))]
5597#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5598pub unsafe fn Q6_P_cmpynac_RR_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
5599    hexagon_M2_cnacs_s0(rxx, rs, rt)
5600}
5601
5602/// `Rxx32-=cmpy(Rs32,Rt32):<<1:sat`
5603///
5604/// Instruction Type: M
5605/// Execution Slots: SLOT23
5606#[inline(always)]
5607#[cfg_attr(test, assert_instr(cmpy))]
5608#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5609pub unsafe fn Q6_P_cmpynac_RR_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
5610    hexagon_M2_cnacs_s1(rxx, rs, rt)
5611}
5612
5613/// `Rxx32-=cmpy(Rs32,Rt32*):sat`
5614///
5615/// Instruction Type: M
5616/// Execution Slots: SLOT23
5617#[inline(always)]
5618#[cfg_attr(test, assert_instr(cmpy))]
5619#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5620pub unsafe fn Q6_P_cmpynac_RR_conj_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
5621    hexagon_M2_cnacsc_s0(rxx, rs, rt)
5622}
5623
5624/// `Rxx32-=cmpy(Rs32,Rt32*):<<1:sat`
5625///
5626/// Instruction Type: M
5627/// Execution Slots: SLOT23
5628#[inline(always)]
5629#[cfg_attr(test, assert_instr(cmpy))]
5630#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5631pub unsafe fn Q6_P_cmpynac_RR_conj_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
5632    hexagon_M2_cnacsc_s1(rxx, rs, rt)
5633}
5634
5635/// `Rxx32+=mpy(Rs32,Rt32)`
5636///
5637/// Instruction Type: M
5638/// Execution Slots: SLOT23
5639#[inline(always)]
5640#[cfg_attr(test, assert_instr(mpy))]
5641#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5642pub unsafe fn Q6_P_mpyacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
5643    hexagon_M2_dpmpyss_acc_s0(rxx, rs, rt)
5644}
5645
5646/// `Rxx32-=mpy(Rs32,Rt32)`
5647///
5648/// Instruction Type: M
5649/// Execution Slots: SLOT23
5650#[inline(always)]
5651#[cfg_attr(test, assert_instr(mpy))]
5652#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5653pub unsafe fn Q6_P_mpynac_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
5654    hexagon_M2_dpmpyss_nac_s0(rxx, rs, rt)
5655}
5656
5657/// `Rd32=mpy(Rs32,Rt32):rnd`
5658///
5659/// Instruction Type: M
5660/// Execution Slots: SLOT23
5661#[inline(always)]
5662#[cfg_attr(test, assert_instr(mpy))]
5663#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5664pub unsafe fn Q6_R_mpy_RR_rnd(rs: i32, rt: i32) -> i32 {
5665    hexagon_M2_dpmpyss_rnd_s0(rs, rt)
5666}
5667
5668/// `Rdd32=mpy(Rs32,Rt32)`
5669///
5670/// Instruction Type: M
5671/// Execution Slots: SLOT23
5672#[inline(always)]
5673#[cfg_attr(test, assert_instr(mpy))]
5674#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5675pub unsafe fn Q6_P_mpy_RR(rs: i32, rt: i32) -> i64 {
5676    hexagon_M2_dpmpyss_s0(rs, rt)
5677}
5678
5679/// `Rxx32+=mpyu(Rs32,Rt32)`
5680///
5681/// Instruction Type: M
5682/// Execution Slots: SLOT23
5683#[inline(always)]
5684#[cfg_attr(test, assert_instr(mpyu))]
5685#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5686pub unsafe fn Q6_P_mpyuacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
5687    hexagon_M2_dpmpyuu_acc_s0(rxx, rs, rt)
5688}
5689
5690/// `Rxx32-=mpyu(Rs32,Rt32)`
5691///
5692/// Instruction Type: M
5693/// Execution Slots: SLOT23
5694#[inline(always)]
5695#[cfg_attr(test, assert_instr(mpyu))]
5696#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5697pub unsafe fn Q6_P_mpyunac_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
5698    hexagon_M2_dpmpyuu_nac_s0(rxx, rs, rt)
5699}
5700
5701/// `Rdd32=mpyu(Rs32,Rt32)`
5702///
5703/// Instruction Type: M
5704/// Execution Slots: SLOT23
5705#[inline(always)]
5706#[cfg_attr(test, assert_instr(mpyu))]
5707#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5708pub unsafe fn Q6_P_mpyu_RR(rs: i32, rt: i32) -> i64 {
5709    hexagon_M2_dpmpyuu_s0(rs, rt)
5710}
5711
5712/// `Rd32=mpy(Rs32,Rt32.h):<<1:rnd:sat`
5713///
5714/// Instruction Type: M
5715/// Execution Slots: SLOT23
5716#[inline(always)]
5717#[cfg_attr(test, assert_instr(mpy))]
5718#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5719pub unsafe fn Q6_R_mpy_RRh_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
5720    hexagon_M2_hmmpyh_rs1(rs, rt)
5721}
5722
5723/// `Rd32=mpy(Rs32,Rt32.h):<<1:sat`
5724///
5725/// Instruction Type: M
5726/// Execution Slots: SLOT23
5727#[inline(always)]
5728#[cfg_attr(test, assert_instr(mpy))]
5729#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5730pub unsafe fn Q6_R_mpy_RRh_s1_sat(rs: i32, rt: i32) -> i32 {
5731    hexagon_M2_hmmpyh_s1(rs, rt)
5732}
5733
5734/// `Rd32=mpy(Rs32,Rt32.l):<<1:rnd:sat`
5735///
5736/// Instruction Type: M
5737/// Execution Slots: SLOT23
5738#[inline(always)]
5739#[cfg_attr(test, assert_instr(mpy))]
5740#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5741pub unsafe fn Q6_R_mpy_RRl_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
5742    hexagon_M2_hmmpyl_rs1(rs, rt)
5743}
5744
5745/// `Rd32=mpy(Rs32,Rt32.l):<<1:sat`
5746///
5747/// Instruction Type: M
5748/// Execution Slots: SLOT23
5749#[inline(always)]
5750#[cfg_attr(test, assert_instr(mpy))]
5751#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5752pub unsafe fn Q6_R_mpy_RRl_s1_sat(rs: i32, rt: i32) -> i32 {
5753    hexagon_M2_hmmpyl_s1(rs, rt)
5754}
5755
5756/// `Rx32+=mpyi(Rs32,Rt32)`
5757///
5758/// Instruction Type: M
5759/// Execution Slots: SLOT23
5760#[inline(always)]
5761#[cfg_attr(test, assert_instr(mpyi))]
5762#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5763pub unsafe fn Q6_R_mpyiacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
5764    hexagon_M2_maci(rx, rs, rt)
5765}
5766
5767/// `Rx32-=mpyi(Rs32,#u8)`
5768///
5769/// Instruction Type: M
5770/// Execution Slots: SLOT23
5771#[inline(always)]
5772#[rustc_legacy_const_generics(2)]
5773#[cfg_attr(test, assert_instr(mpyi, IU8 = 0))]
5774#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5775pub unsafe fn Q6_R_mpyinac_RI<const IU8: u32>(rx: i32, rs: i32) -> i32 {
5776    static_assert_uimm_bits!(IU8, 8);
5777    hexagon_M2_macsin(rx, rs, IU8 as i32)
5778}
5779
5780/// `Rx32+=mpyi(Rs32,#u8)`
5781///
5782/// Instruction Type: M
5783/// Execution Slots: SLOT23
5784#[inline(always)]
5785#[rustc_legacy_const_generics(2)]
5786#[cfg_attr(test, assert_instr(mpyi, IU8 = 0))]
5787#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5788pub unsafe fn Q6_R_mpyiacc_RI<const IU8: u32>(rx: i32, rs: i32) -> i32 {
5789    static_assert_uimm_bits!(IU8, 8);
5790    hexagon_M2_macsip(rx, rs, IU8 as i32)
5791}
5792
5793/// `Rxx32+=vmpywoh(Rss32,Rtt32):rnd:sat`
5794///
5795/// Instruction Type: M
5796/// Execution Slots: SLOT23
5797#[inline(always)]
5798#[cfg_attr(test, assert_instr(vmpywoh))]
5799#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5800pub unsafe fn Q6_P_vmpywohacc_PP_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5801    hexagon_M2_mmachs_rs0(rxx, rss, rtt)
5802}
5803
5804/// `Rxx32+=vmpywoh(Rss32,Rtt32):<<1:rnd:sat`
5805///
5806/// Instruction Type: M
5807/// Execution Slots: SLOT23
5808#[inline(always)]
5809#[cfg_attr(test, assert_instr(vmpywoh))]
5810#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5811pub unsafe fn Q6_P_vmpywohacc_PP_s1_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5812    hexagon_M2_mmachs_rs1(rxx, rss, rtt)
5813}
5814
5815/// `Rxx32+=vmpywoh(Rss32,Rtt32):sat`
5816///
5817/// Instruction Type: M
5818/// Execution Slots: SLOT23
5819#[inline(always)]
5820#[cfg_attr(test, assert_instr(vmpywoh))]
5821#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5822pub unsafe fn Q6_P_vmpywohacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5823    hexagon_M2_mmachs_s0(rxx, rss, rtt)
5824}
5825
5826/// `Rxx32+=vmpywoh(Rss32,Rtt32):<<1:sat`
5827///
5828/// Instruction Type: M
5829/// Execution Slots: SLOT23
5830#[inline(always)]
5831#[cfg_attr(test, assert_instr(vmpywoh))]
5832#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5833pub unsafe fn Q6_P_vmpywohacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5834    hexagon_M2_mmachs_s1(rxx, rss, rtt)
5835}
5836
5837/// `Rxx32+=vmpyweh(Rss32,Rtt32):rnd:sat`
5838///
5839/// Instruction Type: M
5840/// Execution Slots: SLOT23
5841#[inline(always)]
5842#[cfg_attr(test, assert_instr(vmpyweh))]
5843#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5844pub unsafe fn Q6_P_vmpywehacc_PP_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5845    hexagon_M2_mmacls_rs0(rxx, rss, rtt)
5846}
5847
5848/// `Rxx32+=vmpyweh(Rss32,Rtt32):<<1:rnd:sat`
5849///
5850/// Instruction Type: M
5851/// Execution Slots: SLOT23
5852#[inline(always)]
5853#[cfg_attr(test, assert_instr(vmpyweh))]
5854#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5855pub unsafe fn Q6_P_vmpywehacc_PP_s1_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5856    hexagon_M2_mmacls_rs1(rxx, rss, rtt)
5857}
5858
5859/// `Rxx32+=vmpyweh(Rss32,Rtt32):sat`
5860///
5861/// Instruction Type: M
5862/// Execution Slots: SLOT23
5863#[inline(always)]
5864#[cfg_attr(test, assert_instr(vmpyweh))]
5865#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5866pub unsafe fn Q6_P_vmpywehacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5867    hexagon_M2_mmacls_s0(rxx, rss, rtt)
5868}
5869
5870/// `Rxx32+=vmpyweh(Rss32,Rtt32):<<1:sat`
5871///
5872/// Instruction Type: M
5873/// Execution Slots: SLOT23
5874#[inline(always)]
5875#[cfg_attr(test, assert_instr(vmpyweh))]
5876#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5877pub unsafe fn Q6_P_vmpywehacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5878    hexagon_M2_mmacls_s1(rxx, rss, rtt)
5879}
5880
5881/// `Rxx32+=vmpywouh(Rss32,Rtt32):rnd:sat`
5882///
5883/// Instruction Type: M
5884/// Execution Slots: SLOT23
5885#[inline(always)]
5886#[cfg_attr(test, assert_instr(vmpywouh))]
5887#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5888pub unsafe fn Q6_P_vmpywouhacc_PP_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5889    hexagon_M2_mmacuhs_rs0(rxx, rss, rtt)
5890}
5891
5892/// `Rxx32+=vmpywouh(Rss32,Rtt32):<<1:rnd:sat`
5893///
5894/// Instruction Type: M
5895/// Execution Slots: SLOT23
5896#[inline(always)]
5897#[cfg_attr(test, assert_instr(vmpywouh))]
5898#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5899pub unsafe fn Q6_P_vmpywouhacc_PP_s1_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5900    hexagon_M2_mmacuhs_rs1(rxx, rss, rtt)
5901}
5902
5903/// `Rxx32+=vmpywouh(Rss32,Rtt32):sat`
5904///
5905/// Instruction Type: M
5906/// Execution Slots: SLOT23
5907#[inline(always)]
5908#[cfg_attr(test, assert_instr(vmpywouh))]
5909#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5910pub unsafe fn Q6_P_vmpywouhacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5911    hexagon_M2_mmacuhs_s0(rxx, rss, rtt)
5912}
5913
5914/// `Rxx32+=vmpywouh(Rss32,Rtt32):<<1:sat`
5915///
5916/// Instruction Type: M
5917/// Execution Slots: SLOT23
5918#[inline(always)]
5919#[cfg_attr(test, assert_instr(vmpywouh))]
5920#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5921pub unsafe fn Q6_P_vmpywouhacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5922    hexagon_M2_mmacuhs_s1(rxx, rss, rtt)
5923}
5924
5925/// `Rxx32+=vmpyweuh(Rss32,Rtt32):rnd:sat`
5926///
5927/// Instruction Type: M
5928/// Execution Slots: SLOT23
5929#[inline(always)]
5930#[cfg_attr(test, assert_instr(vmpyweuh))]
5931#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5932pub unsafe fn Q6_P_vmpyweuhacc_PP_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5933    hexagon_M2_mmaculs_rs0(rxx, rss, rtt)
5934}
5935
5936/// `Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat`
5937///
5938/// Instruction Type: M
5939/// Execution Slots: SLOT23
5940#[inline(always)]
5941#[cfg_attr(test, assert_instr(vmpyweuh))]
5942#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5943pub unsafe fn Q6_P_vmpyweuhacc_PP_s1_rnd_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5944    hexagon_M2_mmaculs_rs1(rxx, rss, rtt)
5945}
5946
5947/// `Rxx32+=vmpyweuh(Rss32,Rtt32):sat`
5948///
5949/// Instruction Type: M
5950/// Execution Slots: SLOT23
5951#[inline(always)]
5952#[cfg_attr(test, assert_instr(vmpyweuh))]
5953#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5954pub unsafe fn Q6_P_vmpyweuhacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5955    hexagon_M2_mmaculs_s0(rxx, rss, rtt)
5956}
5957
5958/// `Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:sat`
5959///
5960/// Instruction Type: M
5961/// Execution Slots: SLOT23
5962#[inline(always)]
5963#[cfg_attr(test, assert_instr(vmpyweuh))]
5964#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5965pub unsafe fn Q6_P_vmpyweuhacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
5966    hexagon_M2_mmaculs_s1(rxx, rss, rtt)
5967}
5968
5969/// `Rdd32=vmpywoh(Rss32,Rtt32):rnd:sat`
5970///
5971/// Instruction Type: M
5972/// Execution Slots: SLOT23
5973#[inline(always)]
5974#[cfg_attr(test, assert_instr(vmpywoh))]
5975#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5976pub unsafe fn Q6_P_vmpywoh_PP_rnd_sat(rss: i64, rtt: i64) -> i64 {
5977    hexagon_M2_mmpyh_rs0(rss, rtt)
5978}
5979
5980/// `Rdd32=vmpywoh(Rss32,Rtt32):<<1:rnd:sat`
5981///
5982/// Instruction Type: M
5983/// Execution Slots: SLOT23
5984#[inline(always)]
5985#[cfg_attr(test, assert_instr(vmpywoh))]
5986#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5987pub unsafe fn Q6_P_vmpywoh_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i64 {
5988    hexagon_M2_mmpyh_rs1(rss, rtt)
5989}
5990
5991/// `Rdd32=vmpywoh(Rss32,Rtt32):sat`
5992///
5993/// Instruction Type: M
5994/// Execution Slots: SLOT23
5995#[inline(always)]
5996#[cfg_attr(test, assert_instr(vmpywoh))]
5997#[unstable(feature = "stdarch_hexagon", issue = "151523")]
5998pub unsafe fn Q6_P_vmpywoh_PP_sat(rss: i64, rtt: i64) -> i64 {
5999    hexagon_M2_mmpyh_s0(rss, rtt)
6000}
6001
6002/// `Rdd32=vmpywoh(Rss32,Rtt32):<<1:sat`
6003///
6004/// Instruction Type: M
6005/// Execution Slots: SLOT23
6006#[inline(always)]
6007#[cfg_attr(test, assert_instr(vmpywoh))]
6008#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6009pub unsafe fn Q6_P_vmpywoh_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
6010    hexagon_M2_mmpyh_s1(rss, rtt)
6011}
6012
6013/// `Rdd32=vmpyweh(Rss32,Rtt32):rnd:sat`
6014///
6015/// Instruction Type: M
6016/// Execution Slots: SLOT23
6017#[inline(always)]
6018#[cfg_attr(test, assert_instr(vmpyweh))]
6019#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6020pub unsafe fn Q6_P_vmpyweh_PP_rnd_sat(rss: i64, rtt: i64) -> i64 {
6021    hexagon_M2_mmpyl_rs0(rss, rtt)
6022}
6023
6024/// `Rdd32=vmpyweh(Rss32,Rtt32):<<1:rnd:sat`
6025///
6026/// Instruction Type: M
6027/// Execution Slots: SLOT23
6028#[inline(always)]
6029#[cfg_attr(test, assert_instr(vmpyweh))]
6030#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6031pub unsafe fn Q6_P_vmpyweh_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i64 {
6032    hexagon_M2_mmpyl_rs1(rss, rtt)
6033}
6034
6035/// `Rdd32=vmpyweh(Rss32,Rtt32):sat`
6036///
6037/// Instruction Type: M
6038/// Execution Slots: SLOT23
6039#[inline(always)]
6040#[cfg_attr(test, assert_instr(vmpyweh))]
6041#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6042pub unsafe fn Q6_P_vmpyweh_PP_sat(rss: i64, rtt: i64) -> i64 {
6043    hexagon_M2_mmpyl_s0(rss, rtt)
6044}
6045
6046/// `Rdd32=vmpyweh(Rss32,Rtt32):<<1:sat`
6047///
6048/// Instruction Type: M
6049/// Execution Slots: SLOT23
6050#[inline(always)]
6051#[cfg_attr(test, assert_instr(vmpyweh))]
6052#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6053pub unsafe fn Q6_P_vmpyweh_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
6054    hexagon_M2_mmpyl_s1(rss, rtt)
6055}
6056
6057/// `Rdd32=vmpywouh(Rss32,Rtt32):rnd:sat`
6058///
6059/// Instruction Type: M
6060/// Execution Slots: SLOT23
6061#[inline(always)]
6062#[cfg_attr(test, assert_instr(vmpywouh))]
6063#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6064pub unsafe fn Q6_P_vmpywouh_PP_rnd_sat(rss: i64, rtt: i64) -> i64 {
6065    hexagon_M2_mmpyuh_rs0(rss, rtt)
6066}
6067
6068/// `Rdd32=vmpywouh(Rss32,Rtt32):<<1:rnd:sat`
6069///
6070/// Instruction Type: M
6071/// Execution Slots: SLOT23
6072#[inline(always)]
6073#[cfg_attr(test, assert_instr(vmpywouh))]
6074#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6075pub unsafe fn Q6_P_vmpywouh_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i64 {
6076    hexagon_M2_mmpyuh_rs1(rss, rtt)
6077}
6078
6079/// `Rdd32=vmpywouh(Rss32,Rtt32):sat`
6080///
6081/// Instruction Type: M
6082/// Execution Slots: SLOT23
6083#[inline(always)]
6084#[cfg_attr(test, assert_instr(vmpywouh))]
6085#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6086pub unsafe fn Q6_P_vmpywouh_PP_sat(rss: i64, rtt: i64) -> i64 {
6087    hexagon_M2_mmpyuh_s0(rss, rtt)
6088}
6089
6090/// `Rdd32=vmpywouh(Rss32,Rtt32):<<1:sat`
6091///
6092/// Instruction Type: M
6093/// Execution Slots: SLOT23
6094#[inline(always)]
6095#[cfg_attr(test, assert_instr(vmpywouh))]
6096#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6097pub unsafe fn Q6_P_vmpywouh_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
6098    hexagon_M2_mmpyuh_s1(rss, rtt)
6099}
6100
6101/// `Rdd32=vmpyweuh(Rss32,Rtt32):rnd:sat`
6102///
6103/// Instruction Type: M
6104/// Execution Slots: SLOT23
6105#[inline(always)]
6106#[cfg_attr(test, assert_instr(vmpyweuh))]
6107#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6108pub unsafe fn Q6_P_vmpyweuh_PP_rnd_sat(rss: i64, rtt: i64) -> i64 {
6109    hexagon_M2_mmpyul_rs0(rss, rtt)
6110}
6111
6112/// `Rdd32=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat`
6113///
6114/// Instruction Type: M
6115/// Execution Slots: SLOT23
6116#[inline(always)]
6117#[cfg_attr(test, assert_instr(vmpyweuh))]
6118#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6119pub unsafe fn Q6_P_vmpyweuh_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i64 {
6120    hexagon_M2_mmpyul_rs1(rss, rtt)
6121}
6122
6123/// `Rdd32=vmpyweuh(Rss32,Rtt32):sat`
6124///
6125/// Instruction Type: M
6126/// Execution Slots: SLOT23
6127#[inline(always)]
6128#[cfg_attr(test, assert_instr(vmpyweuh))]
6129#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6130pub unsafe fn Q6_P_vmpyweuh_PP_sat(rss: i64, rtt: i64) -> i64 {
6131    hexagon_M2_mmpyul_s0(rss, rtt)
6132}
6133
6134/// `Rdd32=vmpyweuh(Rss32,Rtt32):<<1:sat`
6135///
6136/// Instruction Type: M
6137/// Execution Slots: SLOT23
6138#[inline(always)]
6139#[cfg_attr(test, assert_instr(vmpyweuh))]
6140#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6141pub unsafe fn Q6_P_vmpyweuh_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
6142    hexagon_M2_mmpyul_s1(rss, rtt)
6143}
6144
6145/// `Rx32+=mpy(Rs32.h,Rt32.h)`
6146///
6147/// Instruction Type: M
6148/// Execution Slots: SLOT23
6149#[inline(always)]
6150#[cfg_attr(test, assert_instr(mpy))]
6151#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6152pub unsafe fn Q6_R_mpyacc_RhRh(rx: i32, rs: i32, rt: i32) -> i32 {
6153    hexagon_M2_mpy_acc_hh_s0(rx, rs, rt)
6154}
6155
6156/// `Rx32+=mpy(Rs32.h,Rt32.h):<<1`
6157///
6158/// Instruction Type: M
6159/// Execution Slots: SLOT23
6160#[inline(always)]
6161#[cfg_attr(test, assert_instr(mpy))]
6162#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6163pub unsafe fn Q6_R_mpyacc_RhRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
6164    hexagon_M2_mpy_acc_hh_s1(rx, rs, rt)
6165}
6166
6167/// `Rx32+=mpy(Rs32.h,Rt32.l)`
6168///
6169/// Instruction Type: M
6170/// Execution Slots: SLOT23
6171#[inline(always)]
6172#[cfg_attr(test, assert_instr(mpy))]
6173#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6174pub unsafe fn Q6_R_mpyacc_RhRl(rx: i32, rs: i32, rt: i32) -> i32 {
6175    hexagon_M2_mpy_acc_hl_s0(rx, rs, rt)
6176}
6177
6178/// `Rx32+=mpy(Rs32.h,Rt32.l):<<1`
6179///
6180/// Instruction Type: M
6181/// Execution Slots: SLOT23
6182#[inline(always)]
6183#[cfg_attr(test, assert_instr(mpy))]
6184#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6185pub unsafe fn Q6_R_mpyacc_RhRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
6186    hexagon_M2_mpy_acc_hl_s1(rx, rs, rt)
6187}
6188
6189/// `Rx32+=mpy(Rs32.l,Rt32.h)`
6190///
6191/// Instruction Type: M
6192/// Execution Slots: SLOT23
6193#[inline(always)]
6194#[cfg_attr(test, assert_instr(mpy))]
6195#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6196pub unsafe fn Q6_R_mpyacc_RlRh(rx: i32, rs: i32, rt: i32) -> i32 {
6197    hexagon_M2_mpy_acc_lh_s0(rx, rs, rt)
6198}
6199
6200/// `Rx32+=mpy(Rs32.l,Rt32.h):<<1`
6201///
6202/// Instruction Type: M
6203/// Execution Slots: SLOT23
6204#[inline(always)]
6205#[cfg_attr(test, assert_instr(mpy))]
6206#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6207pub unsafe fn Q6_R_mpyacc_RlRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
6208    hexagon_M2_mpy_acc_lh_s1(rx, rs, rt)
6209}
6210
6211/// `Rx32+=mpy(Rs32.l,Rt32.l)`
6212///
6213/// Instruction Type: M
6214/// Execution Slots: SLOT23
6215#[inline(always)]
6216#[cfg_attr(test, assert_instr(mpy))]
6217#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6218pub unsafe fn Q6_R_mpyacc_RlRl(rx: i32, rs: i32, rt: i32) -> i32 {
6219    hexagon_M2_mpy_acc_ll_s0(rx, rs, rt)
6220}
6221
6222/// `Rx32+=mpy(Rs32.l,Rt32.l):<<1`
6223///
6224/// Instruction Type: M
6225/// Execution Slots: SLOT23
6226#[inline(always)]
6227#[cfg_attr(test, assert_instr(mpy))]
6228#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6229pub unsafe fn Q6_R_mpyacc_RlRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
6230    hexagon_M2_mpy_acc_ll_s1(rx, rs, rt)
6231}
6232
6233/// `Rx32+=mpy(Rs32.h,Rt32.h):sat`
6234///
6235/// Instruction Type: M
6236/// Execution Slots: SLOT23
6237#[inline(always)]
6238#[cfg_attr(test, assert_instr(mpy))]
6239#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6240pub unsafe fn Q6_R_mpyacc_RhRh_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6241    hexagon_M2_mpy_acc_sat_hh_s0(rx, rs, rt)
6242}
6243
6244/// `Rx32+=mpy(Rs32.h,Rt32.h):<<1:sat`
6245///
6246/// Instruction Type: M
6247/// Execution Slots: SLOT23
6248#[inline(always)]
6249#[cfg_attr(test, assert_instr(mpy))]
6250#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6251pub unsafe fn Q6_R_mpyacc_RhRh_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6252    hexagon_M2_mpy_acc_sat_hh_s1(rx, rs, rt)
6253}
6254
6255/// `Rx32+=mpy(Rs32.h,Rt32.l):sat`
6256///
6257/// Instruction Type: M
6258/// Execution Slots: SLOT23
6259#[inline(always)]
6260#[cfg_attr(test, assert_instr(mpy))]
6261#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6262pub unsafe fn Q6_R_mpyacc_RhRl_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6263    hexagon_M2_mpy_acc_sat_hl_s0(rx, rs, rt)
6264}
6265
6266/// `Rx32+=mpy(Rs32.h,Rt32.l):<<1:sat`
6267///
6268/// Instruction Type: M
6269/// Execution Slots: SLOT23
6270#[inline(always)]
6271#[cfg_attr(test, assert_instr(mpy))]
6272#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6273pub unsafe fn Q6_R_mpyacc_RhRl_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6274    hexagon_M2_mpy_acc_sat_hl_s1(rx, rs, rt)
6275}
6276
6277/// `Rx32+=mpy(Rs32.l,Rt32.h):sat`
6278///
6279/// Instruction Type: M
6280/// Execution Slots: SLOT23
6281#[inline(always)]
6282#[cfg_attr(test, assert_instr(mpy))]
6283#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6284pub unsafe fn Q6_R_mpyacc_RlRh_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6285    hexagon_M2_mpy_acc_sat_lh_s0(rx, rs, rt)
6286}
6287
6288/// `Rx32+=mpy(Rs32.l,Rt32.h):<<1:sat`
6289///
6290/// Instruction Type: M
6291/// Execution Slots: SLOT23
6292#[inline(always)]
6293#[cfg_attr(test, assert_instr(mpy))]
6294#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6295pub unsafe fn Q6_R_mpyacc_RlRh_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6296    hexagon_M2_mpy_acc_sat_lh_s1(rx, rs, rt)
6297}
6298
6299/// `Rx32+=mpy(Rs32.l,Rt32.l):sat`
6300///
6301/// Instruction Type: M
6302/// Execution Slots: SLOT23
6303#[inline(always)]
6304#[cfg_attr(test, assert_instr(mpy))]
6305#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6306pub unsafe fn Q6_R_mpyacc_RlRl_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6307    hexagon_M2_mpy_acc_sat_ll_s0(rx, rs, rt)
6308}
6309
6310/// `Rx32+=mpy(Rs32.l,Rt32.l):<<1:sat`
6311///
6312/// Instruction Type: M
6313/// Execution Slots: SLOT23
6314#[inline(always)]
6315#[cfg_attr(test, assert_instr(mpy))]
6316#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6317pub unsafe fn Q6_R_mpyacc_RlRl_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6318    hexagon_M2_mpy_acc_sat_ll_s1(rx, rs, rt)
6319}
6320
6321/// `Rd32=mpy(Rs32.h,Rt32.h)`
6322///
6323/// Instruction Type: M
6324/// Execution Slots: SLOT23
6325#[inline(always)]
6326#[cfg_attr(test, assert_instr(mpy))]
6327#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6328pub unsafe fn Q6_R_mpy_RhRh(rs: i32, rt: i32) -> i32 {
6329    hexagon_M2_mpy_hh_s0(rs, rt)
6330}
6331
6332/// `Rd32=mpy(Rs32.h,Rt32.h):<<1`
6333///
6334/// Instruction Type: M
6335/// Execution Slots: SLOT23
6336#[inline(always)]
6337#[cfg_attr(test, assert_instr(mpy))]
6338#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6339pub unsafe fn Q6_R_mpy_RhRh_s1(rs: i32, rt: i32) -> i32 {
6340    hexagon_M2_mpy_hh_s1(rs, rt)
6341}
6342
6343/// `Rd32=mpy(Rs32.h,Rt32.l)`
6344///
6345/// Instruction Type: M
6346/// Execution Slots: SLOT23
6347#[inline(always)]
6348#[cfg_attr(test, assert_instr(mpy))]
6349#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6350pub unsafe fn Q6_R_mpy_RhRl(rs: i32, rt: i32) -> i32 {
6351    hexagon_M2_mpy_hl_s0(rs, rt)
6352}
6353
6354/// `Rd32=mpy(Rs32.h,Rt32.l):<<1`
6355///
6356/// Instruction Type: M
6357/// Execution Slots: SLOT23
6358#[inline(always)]
6359#[cfg_attr(test, assert_instr(mpy))]
6360#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6361pub unsafe fn Q6_R_mpy_RhRl_s1(rs: i32, rt: i32) -> i32 {
6362    hexagon_M2_mpy_hl_s1(rs, rt)
6363}
6364
6365/// `Rd32=mpy(Rs32.l,Rt32.h)`
6366///
6367/// Instruction Type: M
6368/// Execution Slots: SLOT23
6369#[inline(always)]
6370#[cfg_attr(test, assert_instr(mpy))]
6371#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6372pub unsafe fn Q6_R_mpy_RlRh(rs: i32, rt: i32) -> i32 {
6373    hexagon_M2_mpy_lh_s0(rs, rt)
6374}
6375
6376/// `Rd32=mpy(Rs32.l,Rt32.h):<<1`
6377///
6378/// Instruction Type: M
6379/// Execution Slots: SLOT23
6380#[inline(always)]
6381#[cfg_attr(test, assert_instr(mpy))]
6382#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6383pub unsafe fn Q6_R_mpy_RlRh_s1(rs: i32, rt: i32) -> i32 {
6384    hexagon_M2_mpy_lh_s1(rs, rt)
6385}
6386
6387/// `Rd32=mpy(Rs32.l,Rt32.l)`
6388///
6389/// Instruction Type: M
6390/// Execution Slots: SLOT23
6391#[inline(always)]
6392#[cfg_attr(test, assert_instr(mpy))]
6393#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6394pub unsafe fn Q6_R_mpy_RlRl(rs: i32, rt: i32) -> i32 {
6395    hexagon_M2_mpy_ll_s0(rs, rt)
6396}
6397
6398/// `Rd32=mpy(Rs32.l,Rt32.l):<<1`
6399///
6400/// Instruction Type: M
6401/// Execution Slots: SLOT23
6402#[inline(always)]
6403#[cfg_attr(test, assert_instr(mpy))]
6404#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6405pub unsafe fn Q6_R_mpy_RlRl_s1(rs: i32, rt: i32) -> i32 {
6406    hexagon_M2_mpy_ll_s1(rs, rt)
6407}
6408
6409/// `Rx32-=mpy(Rs32.h,Rt32.h)`
6410///
6411/// Instruction Type: M
6412/// Execution Slots: SLOT23
6413#[inline(always)]
6414#[cfg_attr(test, assert_instr(mpy))]
6415#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6416pub unsafe fn Q6_R_mpynac_RhRh(rx: i32, rs: i32, rt: i32) -> i32 {
6417    hexagon_M2_mpy_nac_hh_s0(rx, rs, rt)
6418}
6419
6420/// `Rx32-=mpy(Rs32.h,Rt32.h):<<1`
6421///
6422/// Instruction Type: M
6423/// Execution Slots: SLOT23
6424#[inline(always)]
6425#[cfg_attr(test, assert_instr(mpy))]
6426#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6427pub unsafe fn Q6_R_mpynac_RhRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
6428    hexagon_M2_mpy_nac_hh_s1(rx, rs, rt)
6429}
6430
6431/// `Rx32-=mpy(Rs32.h,Rt32.l)`
6432///
6433/// Instruction Type: M
6434/// Execution Slots: SLOT23
6435#[inline(always)]
6436#[cfg_attr(test, assert_instr(mpy))]
6437#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6438pub unsafe fn Q6_R_mpynac_RhRl(rx: i32, rs: i32, rt: i32) -> i32 {
6439    hexagon_M2_mpy_nac_hl_s0(rx, rs, rt)
6440}
6441
6442/// `Rx32-=mpy(Rs32.h,Rt32.l):<<1`
6443///
6444/// Instruction Type: M
6445/// Execution Slots: SLOT23
6446#[inline(always)]
6447#[cfg_attr(test, assert_instr(mpy))]
6448#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6449pub unsafe fn Q6_R_mpynac_RhRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
6450    hexagon_M2_mpy_nac_hl_s1(rx, rs, rt)
6451}
6452
6453/// `Rx32-=mpy(Rs32.l,Rt32.h)`
6454///
6455/// Instruction Type: M
6456/// Execution Slots: SLOT23
6457#[inline(always)]
6458#[cfg_attr(test, assert_instr(mpy))]
6459#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6460pub unsafe fn Q6_R_mpynac_RlRh(rx: i32, rs: i32, rt: i32) -> i32 {
6461    hexagon_M2_mpy_nac_lh_s0(rx, rs, rt)
6462}
6463
6464/// `Rx32-=mpy(Rs32.l,Rt32.h):<<1`
6465///
6466/// Instruction Type: M
6467/// Execution Slots: SLOT23
6468#[inline(always)]
6469#[cfg_attr(test, assert_instr(mpy))]
6470#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6471pub unsafe fn Q6_R_mpynac_RlRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
6472    hexagon_M2_mpy_nac_lh_s1(rx, rs, rt)
6473}
6474
6475/// `Rx32-=mpy(Rs32.l,Rt32.l)`
6476///
6477/// Instruction Type: M
6478/// Execution Slots: SLOT23
6479#[inline(always)]
6480#[cfg_attr(test, assert_instr(mpy))]
6481#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6482pub unsafe fn Q6_R_mpynac_RlRl(rx: i32, rs: i32, rt: i32) -> i32 {
6483    hexagon_M2_mpy_nac_ll_s0(rx, rs, rt)
6484}
6485
6486/// `Rx32-=mpy(Rs32.l,Rt32.l):<<1`
6487///
6488/// Instruction Type: M
6489/// Execution Slots: SLOT23
6490#[inline(always)]
6491#[cfg_attr(test, assert_instr(mpy))]
6492#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6493pub unsafe fn Q6_R_mpynac_RlRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
6494    hexagon_M2_mpy_nac_ll_s1(rx, rs, rt)
6495}
6496
6497/// `Rx32-=mpy(Rs32.h,Rt32.h):sat`
6498///
6499/// Instruction Type: M
6500/// Execution Slots: SLOT23
6501#[inline(always)]
6502#[cfg_attr(test, assert_instr(mpy))]
6503#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6504pub unsafe fn Q6_R_mpynac_RhRh_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6505    hexagon_M2_mpy_nac_sat_hh_s0(rx, rs, rt)
6506}
6507
6508/// `Rx32-=mpy(Rs32.h,Rt32.h):<<1:sat`
6509///
6510/// Instruction Type: M
6511/// Execution Slots: SLOT23
6512#[inline(always)]
6513#[cfg_attr(test, assert_instr(mpy))]
6514#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6515pub unsafe fn Q6_R_mpynac_RhRh_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6516    hexagon_M2_mpy_nac_sat_hh_s1(rx, rs, rt)
6517}
6518
6519/// `Rx32-=mpy(Rs32.h,Rt32.l):sat`
6520///
6521/// Instruction Type: M
6522/// Execution Slots: SLOT23
6523#[inline(always)]
6524#[cfg_attr(test, assert_instr(mpy))]
6525#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6526pub unsafe fn Q6_R_mpynac_RhRl_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6527    hexagon_M2_mpy_nac_sat_hl_s0(rx, rs, rt)
6528}
6529
6530/// `Rx32-=mpy(Rs32.h,Rt32.l):<<1:sat`
6531///
6532/// Instruction Type: M
6533/// Execution Slots: SLOT23
6534#[inline(always)]
6535#[cfg_attr(test, assert_instr(mpy))]
6536#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6537pub unsafe fn Q6_R_mpynac_RhRl_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6538    hexagon_M2_mpy_nac_sat_hl_s1(rx, rs, rt)
6539}
6540
6541/// `Rx32-=mpy(Rs32.l,Rt32.h):sat`
6542///
6543/// Instruction Type: M
6544/// Execution Slots: SLOT23
6545#[inline(always)]
6546#[cfg_attr(test, assert_instr(mpy))]
6547#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6548pub unsafe fn Q6_R_mpynac_RlRh_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6549    hexagon_M2_mpy_nac_sat_lh_s0(rx, rs, rt)
6550}
6551
6552/// `Rx32-=mpy(Rs32.l,Rt32.h):<<1:sat`
6553///
6554/// Instruction Type: M
6555/// Execution Slots: SLOT23
6556#[inline(always)]
6557#[cfg_attr(test, assert_instr(mpy))]
6558#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6559pub unsafe fn Q6_R_mpynac_RlRh_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6560    hexagon_M2_mpy_nac_sat_lh_s1(rx, rs, rt)
6561}
6562
6563/// `Rx32-=mpy(Rs32.l,Rt32.l):sat`
6564///
6565/// Instruction Type: M
6566/// Execution Slots: SLOT23
6567#[inline(always)]
6568#[cfg_attr(test, assert_instr(mpy))]
6569#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6570pub unsafe fn Q6_R_mpynac_RlRl_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6571    hexagon_M2_mpy_nac_sat_ll_s0(rx, rs, rt)
6572}
6573
6574/// `Rx32-=mpy(Rs32.l,Rt32.l):<<1:sat`
6575///
6576/// Instruction Type: M
6577/// Execution Slots: SLOT23
6578#[inline(always)]
6579#[cfg_attr(test, assert_instr(mpy))]
6580#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6581pub unsafe fn Q6_R_mpynac_RlRl_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
6582    hexagon_M2_mpy_nac_sat_ll_s1(rx, rs, rt)
6583}
6584
6585/// `Rd32=mpy(Rs32.h,Rt32.h):rnd`
6586///
6587/// Instruction Type: M
6588/// Execution Slots: SLOT23
6589#[inline(always)]
6590#[cfg_attr(test, assert_instr(mpy))]
6591#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6592pub unsafe fn Q6_R_mpy_RhRh_rnd(rs: i32, rt: i32) -> i32 {
6593    hexagon_M2_mpy_rnd_hh_s0(rs, rt)
6594}
6595
6596/// `Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd`
6597///
6598/// Instruction Type: M
6599/// Execution Slots: SLOT23
6600#[inline(always)]
6601#[cfg_attr(test, assert_instr(mpy))]
6602#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6603pub unsafe fn Q6_R_mpy_RhRh_s1_rnd(rs: i32, rt: i32) -> i32 {
6604    hexagon_M2_mpy_rnd_hh_s1(rs, rt)
6605}
6606
6607/// `Rd32=mpy(Rs32.h,Rt32.l):rnd`
6608///
6609/// Instruction Type: M
6610/// Execution Slots: SLOT23
6611#[inline(always)]
6612#[cfg_attr(test, assert_instr(mpy))]
6613#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6614pub unsafe fn Q6_R_mpy_RhRl_rnd(rs: i32, rt: i32) -> i32 {
6615    hexagon_M2_mpy_rnd_hl_s0(rs, rt)
6616}
6617
6618/// `Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd`
6619///
6620/// Instruction Type: M
6621/// Execution Slots: SLOT23
6622#[inline(always)]
6623#[cfg_attr(test, assert_instr(mpy))]
6624#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6625pub unsafe fn Q6_R_mpy_RhRl_s1_rnd(rs: i32, rt: i32) -> i32 {
6626    hexagon_M2_mpy_rnd_hl_s1(rs, rt)
6627}
6628
6629/// `Rd32=mpy(Rs32.l,Rt32.h):rnd`
6630///
6631/// Instruction Type: M
6632/// Execution Slots: SLOT23
6633#[inline(always)]
6634#[cfg_attr(test, assert_instr(mpy))]
6635#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6636pub unsafe fn Q6_R_mpy_RlRh_rnd(rs: i32, rt: i32) -> i32 {
6637    hexagon_M2_mpy_rnd_lh_s0(rs, rt)
6638}
6639
6640/// `Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd`
6641///
6642/// Instruction Type: M
6643/// Execution Slots: SLOT23
6644#[inline(always)]
6645#[cfg_attr(test, assert_instr(mpy))]
6646#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6647pub unsafe fn Q6_R_mpy_RlRh_s1_rnd(rs: i32, rt: i32) -> i32 {
6648    hexagon_M2_mpy_rnd_lh_s1(rs, rt)
6649}
6650
6651/// `Rd32=mpy(Rs32.l,Rt32.l):rnd`
6652///
6653/// Instruction Type: M
6654/// Execution Slots: SLOT23
6655#[inline(always)]
6656#[cfg_attr(test, assert_instr(mpy))]
6657#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6658pub unsafe fn Q6_R_mpy_RlRl_rnd(rs: i32, rt: i32) -> i32 {
6659    hexagon_M2_mpy_rnd_ll_s0(rs, rt)
6660}
6661
6662/// `Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd`
6663///
6664/// Instruction Type: M
6665/// Execution Slots: SLOT23
6666#[inline(always)]
6667#[cfg_attr(test, assert_instr(mpy))]
6668#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6669pub unsafe fn Q6_R_mpy_RlRl_s1_rnd(rs: i32, rt: i32) -> i32 {
6670    hexagon_M2_mpy_rnd_ll_s1(rs, rt)
6671}
6672
6673/// `Rd32=mpy(Rs32.h,Rt32.h):sat`
6674///
6675/// Instruction Type: M
6676/// Execution Slots: SLOT23
6677#[inline(always)]
6678#[cfg_attr(test, assert_instr(mpy))]
6679#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6680pub unsafe fn Q6_R_mpy_RhRh_sat(rs: i32, rt: i32) -> i32 {
6681    hexagon_M2_mpy_sat_hh_s0(rs, rt)
6682}
6683
6684/// `Rd32=mpy(Rs32.h,Rt32.h):<<1:sat`
6685///
6686/// Instruction Type: M
6687/// Execution Slots: SLOT23
6688#[inline(always)]
6689#[cfg_attr(test, assert_instr(mpy))]
6690#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6691pub unsafe fn Q6_R_mpy_RhRh_s1_sat(rs: i32, rt: i32) -> i32 {
6692    hexagon_M2_mpy_sat_hh_s1(rs, rt)
6693}
6694
6695/// `Rd32=mpy(Rs32.h,Rt32.l):sat`
6696///
6697/// Instruction Type: M
6698/// Execution Slots: SLOT23
6699#[inline(always)]
6700#[cfg_attr(test, assert_instr(mpy))]
6701#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6702pub unsafe fn Q6_R_mpy_RhRl_sat(rs: i32, rt: i32) -> i32 {
6703    hexagon_M2_mpy_sat_hl_s0(rs, rt)
6704}
6705
6706/// `Rd32=mpy(Rs32.h,Rt32.l):<<1:sat`
6707///
6708/// Instruction Type: M
6709/// Execution Slots: SLOT23
6710#[inline(always)]
6711#[cfg_attr(test, assert_instr(mpy))]
6712#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6713pub unsafe fn Q6_R_mpy_RhRl_s1_sat(rs: i32, rt: i32) -> i32 {
6714    hexagon_M2_mpy_sat_hl_s1(rs, rt)
6715}
6716
6717/// `Rd32=mpy(Rs32.l,Rt32.h):sat`
6718///
6719/// Instruction Type: M
6720/// Execution Slots: SLOT23
6721#[inline(always)]
6722#[cfg_attr(test, assert_instr(mpy))]
6723#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6724pub unsafe fn Q6_R_mpy_RlRh_sat(rs: i32, rt: i32) -> i32 {
6725    hexagon_M2_mpy_sat_lh_s0(rs, rt)
6726}
6727
6728/// `Rd32=mpy(Rs32.l,Rt32.h):<<1:sat`
6729///
6730/// Instruction Type: M
6731/// Execution Slots: SLOT23
6732#[inline(always)]
6733#[cfg_attr(test, assert_instr(mpy))]
6734#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6735pub unsafe fn Q6_R_mpy_RlRh_s1_sat(rs: i32, rt: i32) -> i32 {
6736    hexagon_M2_mpy_sat_lh_s1(rs, rt)
6737}
6738
6739/// `Rd32=mpy(Rs32.l,Rt32.l):sat`
6740///
6741/// Instruction Type: M
6742/// Execution Slots: SLOT23
6743#[inline(always)]
6744#[cfg_attr(test, assert_instr(mpy))]
6745#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6746pub unsafe fn Q6_R_mpy_RlRl_sat(rs: i32, rt: i32) -> i32 {
6747    hexagon_M2_mpy_sat_ll_s0(rs, rt)
6748}
6749
6750/// `Rd32=mpy(Rs32.l,Rt32.l):<<1:sat`
6751///
6752/// Instruction Type: M
6753/// Execution Slots: SLOT23
6754#[inline(always)]
6755#[cfg_attr(test, assert_instr(mpy))]
6756#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6757pub unsafe fn Q6_R_mpy_RlRl_s1_sat(rs: i32, rt: i32) -> i32 {
6758    hexagon_M2_mpy_sat_ll_s1(rs, rt)
6759}
6760
6761/// `Rd32=mpy(Rs32.h,Rt32.h):rnd:sat`
6762///
6763/// Instruction Type: M
6764/// Execution Slots: SLOT23
6765#[inline(always)]
6766#[cfg_attr(test, assert_instr(mpy))]
6767#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6768pub unsafe fn Q6_R_mpy_RhRh_rnd_sat(rs: i32, rt: i32) -> i32 {
6769    hexagon_M2_mpy_sat_rnd_hh_s0(rs, rt)
6770}
6771
6772/// `Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd:sat`
6773///
6774/// Instruction Type: M
6775/// Execution Slots: SLOT23
6776#[inline(always)]
6777#[cfg_attr(test, assert_instr(mpy))]
6778#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6779pub unsafe fn Q6_R_mpy_RhRh_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
6780    hexagon_M2_mpy_sat_rnd_hh_s1(rs, rt)
6781}
6782
6783/// `Rd32=mpy(Rs32.h,Rt32.l):rnd:sat`
6784///
6785/// Instruction Type: M
6786/// Execution Slots: SLOT23
6787#[inline(always)]
6788#[cfg_attr(test, assert_instr(mpy))]
6789#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6790pub unsafe fn Q6_R_mpy_RhRl_rnd_sat(rs: i32, rt: i32) -> i32 {
6791    hexagon_M2_mpy_sat_rnd_hl_s0(rs, rt)
6792}
6793
6794/// `Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd:sat`
6795///
6796/// Instruction Type: M
6797/// Execution Slots: SLOT23
6798#[inline(always)]
6799#[cfg_attr(test, assert_instr(mpy))]
6800#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6801pub unsafe fn Q6_R_mpy_RhRl_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
6802    hexagon_M2_mpy_sat_rnd_hl_s1(rs, rt)
6803}
6804
6805/// `Rd32=mpy(Rs32.l,Rt32.h):rnd:sat`
6806///
6807/// Instruction Type: M
6808/// Execution Slots: SLOT23
6809#[inline(always)]
6810#[cfg_attr(test, assert_instr(mpy))]
6811#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6812pub unsafe fn Q6_R_mpy_RlRh_rnd_sat(rs: i32, rt: i32) -> i32 {
6813    hexagon_M2_mpy_sat_rnd_lh_s0(rs, rt)
6814}
6815
6816/// `Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd:sat`
6817///
6818/// Instruction Type: M
6819/// Execution Slots: SLOT23
6820#[inline(always)]
6821#[cfg_attr(test, assert_instr(mpy))]
6822#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6823pub unsafe fn Q6_R_mpy_RlRh_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
6824    hexagon_M2_mpy_sat_rnd_lh_s1(rs, rt)
6825}
6826
6827/// `Rd32=mpy(Rs32.l,Rt32.l):rnd:sat`
6828///
6829/// Instruction Type: M
6830/// Execution Slots: SLOT23
6831#[inline(always)]
6832#[cfg_attr(test, assert_instr(mpy))]
6833#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6834pub unsafe fn Q6_R_mpy_RlRl_rnd_sat(rs: i32, rt: i32) -> i32 {
6835    hexagon_M2_mpy_sat_rnd_ll_s0(rs, rt)
6836}
6837
6838/// `Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd:sat`
6839///
6840/// Instruction Type: M
6841/// Execution Slots: SLOT23
6842#[inline(always)]
6843#[cfg_attr(test, assert_instr(mpy))]
6844#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6845pub unsafe fn Q6_R_mpy_RlRl_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
6846    hexagon_M2_mpy_sat_rnd_ll_s1(rs, rt)
6847}
6848
6849/// `Rd32=mpy(Rs32,Rt32)`
6850///
6851/// Instruction Type: M
6852/// Execution Slots: SLOT23
6853#[inline(always)]
6854#[cfg_attr(test, assert_instr(mpy))]
6855#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6856pub unsafe fn Q6_R_mpy_RR(rs: i32, rt: i32) -> i32 {
6857    hexagon_M2_mpy_up(rs, rt)
6858}
6859
6860/// `Rd32=mpy(Rs32,Rt32):<<1`
6861///
6862/// Instruction Type: M
6863/// Execution Slots: SLOT23
6864#[inline(always)]
6865#[cfg_attr(test, assert_instr(mpy))]
6866#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6867pub unsafe fn Q6_R_mpy_RR_s1(rs: i32, rt: i32) -> i32 {
6868    hexagon_M2_mpy_up_s1(rs, rt)
6869}
6870
6871/// `Rd32=mpy(Rs32,Rt32):<<1:sat`
6872///
6873/// Instruction Type: M
6874/// Execution Slots: SLOT23
6875#[inline(always)]
6876#[cfg_attr(test, assert_instr(mpy))]
6877#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6878pub unsafe fn Q6_R_mpy_RR_s1_sat(rs: i32, rt: i32) -> i32 {
6879    hexagon_M2_mpy_up_s1_sat(rs, rt)
6880}
6881
6882/// `Rxx32+=mpy(Rs32.h,Rt32.h)`
6883///
6884/// Instruction Type: M
6885/// Execution Slots: SLOT23
6886#[inline(always)]
6887#[cfg_attr(test, assert_instr(mpy))]
6888#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6889pub unsafe fn Q6_P_mpyacc_RhRh(rxx: i64, rs: i32, rt: i32) -> i64 {
6890    hexagon_M2_mpyd_acc_hh_s0(rxx, rs, rt)
6891}
6892
6893/// `Rxx32+=mpy(Rs32.h,Rt32.h):<<1`
6894///
6895/// Instruction Type: M
6896/// Execution Slots: SLOT23
6897#[inline(always)]
6898#[cfg_attr(test, assert_instr(mpy))]
6899#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6900pub unsafe fn Q6_P_mpyacc_RhRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
6901    hexagon_M2_mpyd_acc_hh_s1(rxx, rs, rt)
6902}
6903
6904/// `Rxx32+=mpy(Rs32.h,Rt32.l)`
6905///
6906/// Instruction Type: M
6907/// Execution Slots: SLOT23
6908#[inline(always)]
6909#[cfg_attr(test, assert_instr(mpy))]
6910#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6911pub unsafe fn Q6_P_mpyacc_RhRl(rxx: i64, rs: i32, rt: i32) -> i64 {
6912    hexagon_M2_mpyd_acc_hl_s0(rxx, rs, rt)
6913}
6914
6915/// `Rxx32+=mpy(Rs32.h,Rt32.l):<<1`
6916///
6917/// Instruction Type: M
6918/// Execution Slots: SLOT23
6919#[inline(always)]
6920#[cfg_attr(test, assert_instr(mpy))]
6921#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6922pub unsafe fn Q6_P_mpyacc_RhRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
6923    hexagon_M2_mpyd_acc_hl_s1(rxx, rs, rt)
6924}
6925
6926/// `Rxx32+=mpy(Rs32.l,Rt32.h)`
6927///
6928/// Instruction Type: M
6929/// Execution Slots: SLOT23
6930#[inline(always)]
6931#[cfg_attr(test, assert_instr(mpy))]
6932#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6933pub unsafe fn Q6_P_mpyacc_RlRh(rxx: i64, rs: i32, rt: i32) -> i64 {
6934    hexagon_M2_mpyd_acc_lh_s0(rxx, rs, rt)
6935}
6936
6937/// `Rxx32+=mpy(Rs32.l,Rt32.h):<<1`
6938///
6939/// Instruction Type: M
6940/// Execution Slots: SLOT23
6941#[inline(always)]
6942#[cfg_attr(test, assert_instr(mpy))]
6943#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6944pub unsafe fn Q6_P_mpyacc_RlRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
6945    hexagon_M2_mpyd_acc_lh_s1(rxx, rs, rt)
6946}
6947
6948/// `Rxx32+=mpy(Rs32.l,Rt32.l)`
6949///
6950/// Instruction Type: M
6951/// Execution Slots: SLOT23
6952#[inline(always)]
6953#[cfg_attr(test, assert_instr(mpy))]
6954#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6955pub unsafe fn Q6_P_mpyacc_RlRl(rxx: i64, rs: i32, rt: i32) -> i64 {
6956    hexagon_M2_mpyd_acc_ll_s0(rxx, rs, rt)
6957}
6958
6959/// `Rxx32+=mpy(Rs32.l,Rt32.l):<<1`
6960///
6961/// Instruction Type: M
6962/// Execution Slots: SLOT23
6963#[inline(always)]
6964#[cfg_attr(test, assert_instr(mpy))]
6965#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6966pub unsafe fn Q6_P_mpyacc_RlRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
6967    hexagon_M2_mpyd_acc_ll_s1(rxx, rs, rt)
6968}
6969
6970/// `Rdd32=mpy(Rs32.h,Rt32.h)`
6971///
6972/// Instruction Type: M
6973/// Execution Slots: SLOT23
6974#[inline(always)]
6975#[cfg_attr(test, assert_instr(mpy))]
6976#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6977pub unsafe fn Q6_P_mpy_RhRh(rs: i32, rt: i32) -> i64 {
6978    hexagon_M2_mpyd_hh_s0(rs, rt)
6979}
6980
6981/// `Rdd32=mpy(Rs32.h,Rt32.h):<<1`
6982///
6983/// Instruction Type: M
6984/// Execution Slots: SLOT23
6985#[inline(always)]
6986#[cfg_attr(test, assert_instr(mpy))]
6987#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6988pub unsafe fn Q6_P_mpy_RhRh_s1(rs: i32, rt: i32) -> i64 {
6989    hexagon_M2_mpyd_hh_s1(rs, rt)
6990}
6991
6992/// `Rdd32=mpy(Rs32.h,Rt32.l)`
6993///
6994/// Instruction Type: M
6995/// Execution Slots: SLOT23
6996#[inline(always)]
6997#[cfg_attr(test, assert_instr(mpy))]
6998#[unstable(feature = "stdarch_hexagon", issue = "151523")]
6999pub unsafe fn Q6_P_mpy_RhRl(rs: i32, rt: i32) -> i64 {
7000    hexagon_M2_mpyd_hl_s0(rs, rt)
7001}
7002
7003/// `Rdd32=mpy(Rs32.h,Rt32.l):<<1`
7004///
7005/// Instruction Type: M
7006/// Execution Slots: SLOT23
7007#[inline(always)]
7008#[cfg_attr(test, assert_instr(mpy))]
7009#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7010pub unsafe fn Q6_P_mpy_RhRl_s1(rs: i32, rt: i32) -> i64 {
7011    hexagon_M2_mpyd_hl_s1(rs, rt)
7012}
7013
7014/// `Rdd32=mpy(Rs32.l,Rt32.h)`
7015///
7016/// Instruction Type: M
7017/// Execution Slots: SLOT23
7018#[inline(always)]
7019#[cfg_attr(test, assert_instr(mpy))]
7020#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7021pub unsafe fn Q6_P_mpy_RlRh(rs: i32, rt: i32) -> i64 {
7022    hexagon_M2_mpyd_lh_s0(rs, rt)
7023}
7024
7025/// `Rdd32=mpy(Rs32.l,Rt32.h):<<1`
7026///
7027/// Instruction Type: M
7028/// Execution Slots: SLOT23
7029#[inline(always)]
7030#[cfg_attr(test, assert_instr(mpy))]
7031#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7032pub unsafe fn Q6_P_mpy_RlRh_s1(rs: i32, rt: i32) -> i64 {
7033    hexagon_M2_mpyd_lh_s1(rs, rt)
7034}
7035
7036/// `Rdd32=mpy(Rs32.l,Rt32.l)`
7037///
7038/// Instruction Type: M
7039/// Execution Slots: SLOT23
7040#[inline(always)]
7041#[cfg_attr(test, assert_instr(mpy))]
7042#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7043pub unsafe fn Q6_P_mpy_RlRl(rs: i32, rt: i32) -> i64 {
7044    hexagon_M2_mpyd_ll_s0(rs, rt)
7045}
7046
7047/// `Rdd32=mpy(Rs32.l,Rt32.l):<<1`
7048///
7049/// Instruction Type: M
7050/// Execution Slots: SLOT23
7051#[inline(always)]
7052#[cfg_attr(test, assert_instr(mpy))]
7053#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7054pub unsafe fn Q6_P_mpy_RlRl_s1(rs: i32, rt: i32) -> i64 {
7055    hexagon_M2_mpyd_ll_s1(rs, rt)
7056}
7057
7058/// `Rxx32-=mpy(Rs32.h,Rt32.h)`
7059///
7060/// Instruction Type: M
7061/// Execution Slots: SLOT23
7062#[inline(always)]
7063#[cfg_attr(test, assert_instr(mpy))]
7064#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7065pub unsafe fn Q6_P_mpynac_RhRh(rxx: i64, rs: i32, rt: i32) -> i64 {
7066    hexagon_M2_mpyd_nac_hh_s0(rxx, rs, rt)
7067}
7068
7069/// `Rxx32-=mpy(Rs32.h,Rt32.h):<<1`
7070///
7071/// Instruction Type: M
7072/// Execution Slots: SLOT23
7073#[inline(always)]
7074#[cfg_attr(test, assert_instr(mpy))]
7075#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7076pub unsafe fn Q6_P_mpynac_RhRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7077    hexagon_M2_mpyd_nac_hh_s1(rxx, rs, rt)
7078}
7079
7080/// `Rxx32-=mpy(Rs32.h,Rt32.l)`
7081///
7082/// Instruction Type: M
7083/// Execution Slots: SLOT23
7084#[inline(always)]
7085#[cfg_attr(test, assert_instr(mpy))]
7086#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7087pub unsafe fn Q6_P_mpynac_RhRl(rxx: i64, rs: i32, rt: i32) -> i64 {
7088    hexagon_M2_mpyd_nac_hl_s0(rxx, rs, rt)
7089}
7090
7091/// `Rxx32-=mpy(Rs32.h,Rt32.l):<<1`
7092///
7093/// Instruction Type: M
7094/// Execution Slots: SLOT23
7095#[inline(always)]
7096#[cfg_attr(test, assert_instr(mpy))]
7097#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7098pub unsafe fn Q6_P_mpynac_RhRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7099    hexagon_M2_mpyd_nac_hl_s1(rxx, rs, rt)
7100}
7101
7102/// `Rxx32-=mpy(Rs32.l,Rt32.h)`
7103///
7104/// Instruction Type: M
7105/// Execution Slots: SLOT23
7106#[inline(always)]
7107#[cfg_attr(test, assert_instr(mpy))]
7108#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7109pub unsafe fn Q6_P_mpynac_RlRh(rxx: i64, rs: i32, rt: i32) -> i64 {
7110    hexagon_M2_mpyd_nac_lh_s0(rxx, rs, rt)
7111}
7112
7113/// `Rxx32-=mpy(Rs32.l,Rt32.h):<<1`
7114///
7115/// Instruction Type: M
7116/// Execution Slots: SLOT23
7117#[inline(always)]
7118#[cfg_attr(test, assert_instr(mpy))]
7119#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7120pub unsafe fn Q6_P_mpynac_RlRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7121    hexagon_M2_mpyd_nac_lh_s1(rxx, rs, rt)
7122}
7123
7124/// `Rxx32-=mpy(Rs32.l,Rt32.l)`
7125///
7126/// Instruction Type: M
7127/// Execution Slots: SLOT23
7128#[inline(always)]
7129#[cfg_attr(test, assert_instr(mpy))]
7130#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7131pub unsafe fn Q6_P_mpynac_RlRl(rxx: i64, rs: i32, rt: i32) -> i64 {
7132    hexagon_M2_mpyd_nac_ll_s0(rxx, rs, rt)
7133}
7134
7135/// `Rxx32-=mpy(Rs32.l,Rt32.l):<<1`
7136///
7137/// Instruction Type: M
7138/// Execution Slots: SLOT23
7139#[inline(always)]
7140#[cfg_attr(test, assert_instr(mpy))]
7141#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7142pub unsafe fn Q6_P_mpynac_RlRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7143    hexagon_M2_mpyd_nac_ll_s1(rxx, rs, rt)
7144}
7145
7146/// `Rdd32=mpy(Rs32.h,Rt32.h):rnd`
7147///
7148/// Instruction Type: M
7149/// Execution Slots: SLOT23
7150#[inline(always)]
7151#[cfg_attr(test, assert_instr(mpy))]
7152#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7153pub unsafe fn Q6_P_mpy_RhRh_rnd(rs: i32, rt: i32) -> i64 {
7154    hexagon_M2_mpyd_rnd_hh_s0(rs, rt)
7155}
7156
7157/// `Rdd32=mpy(Rs32.h,Rt32.h):<<1:rnd`
7158///
7159/// Instruction Type: M
7160/// Execution Slots: SLOT23
7161#[inline(always)]
7162#[cfg_attr(test, assert_instr(mpy))]
7163#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7164pub unsafe fn Q6_P_mpy_RhRh_s1_rnd(rs: i32, rt: i32) -> i64 {
7165    hexagon_M2_mpyd_rnd_hh_s1(rs, rt)
7166}
7167
7168/// `Rdd32=mpy(Rs32.h,Rt32.l):rnd`
7169///
7170/// Instruction Type: M
7171/// Execution Slots: SLOT23
7172#[inline(always)]
7173#[cfg_attr(test, assert_instr(mpy))]
7174#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7175pub unsafe fn Q6_P_mpy_RhRl_rnd(rs: i32, rt: i32) -> i64 {
7176    hexagon_M2_mpyd_rnd_hl_s0(rs, rt)
7177}
7178
7179/// `Rdd32=mpy(Rs32.h,Rt32.l):<<1:rnd`
7180///
7181/// Instruction Type: M
7182/// Execution Slots: SLOT23
7183#[inline(always)]
7184#[cfg_attr(test, assert_instr(mpy))]
7185#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7186pub unsafe fn Q6_P_mpy_RhRl_s1_rnd(rs: i32, rt: i32) -> i64 {
7187    hexagon_M2_mpyd_rnd_hl_s1(rs, rt)
7188}
7189
7190/// `Rdd32=mpy(Rs32.l,Rt32.h):rnd`
7191///
7192/// Instruction Type: M
7193/// Execution Slots: SLOT23
7194#[inline(always)]
7195#[cfg_attr(test, assert_instr(mpy))]
7196#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7197pub unsafe fn Q6_P_mpy_RlRh_rnd(rs: i32, rt: i32) -> i64 {
7198    hexagon_M2_mpyd_rnd_lh_s0(rs, rt)
7199}
7200
7201/// `Rdd32=mpy(Rs32.l,Rt32.h):<<1:rnd`
7202///
7203/// Instruction Type: M
7204/// Execution Slots: SLOT23
7205#[inline(always)]
7206#[cfg_attr(test, assert_instr(mpy))]
7207#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7208pub unsafe fn Q6_P_mpy_RlRh_s1_rnd(rs: i32, rt: i32) -> i64 {
7209    hexagon_M2_mpyd_rnd_lh_s1(rs, rt)
7210}
7211
7212/// `Rdd32=mpy(Rs32.l,Rt32.l):rnd`
7213///
7214/// Instruction Type: M
7215/// Execution Slots: SLOT23
7216#[inline(always)]
7217#[cfg_attr(test, assert_instr(mpy))]
7218#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7219pub unsafe fn Q6_P_mpy_RlRl_rnd(rs: i32, rt: i32) -> i64 {
7220    hexagon_M2_mpyd_rnd_ll_s0(rs, rt)
7221}
7222
7223/// `Rdd32=mpy(Rs32.l,Rt32.l):<<1:rnd`
7224///
7225/// Instruction Type: M
7226/// Execution Slots: SLOT23
7227#[inline(always)]
7228#[cfg_attr(test, assert_instr(mpy))]
7229#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7230pub unsafe fn Q6_P_mpy_RlRl_s1_rnd(rs: i32, rt: i32) -> i64 {
7231    hexagon_M2_mpyd_rnd_ll_s1(rs, rt)
7232}
7233
7234/// `Rd32=mpyi(Rs32,Rt32)`
7235///
7236/// Instruction Type: M
7237/// Execution Slots: SLOT23
7238#[inline(always)]
7239#[cfg_attr(test, assert_instr(mpyi))]
7240#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7241pub unsafe fn Q6_R_mpyi_RR(rs: i32, rt: i32) -> i32 {
7242    hexagon_M2_mpyi(rs, rt)
7243}
7244
7245/// `Rd32=mpyi(Rs32,#m9)`
7246///
7247/// Instruction Type: M
7248/// Execution Slots: SLOT0123
7249#[inline(always)]
7250#[cfg_attr(test, assert_instr(mpyi))]
7251#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7252pub unsafe fn Q6_R_mpyi_RI(rs: i32, im9: i32) -> i32 {
7253    hexagon_M2_mpysmi(rs, im9)
7254}
7255
7256/// `Rd32=mpysu(Rs32,Rt32)`
7257///
7258/// Instruction Type: M
7259/// Execution Slots: SLOT23
7260#[inline(always)]
7261#[cfg_attr(test, assert_instr(mpysu))]
7262#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7263pub unsafe fn Q6_R_mpysu_RR(rs: i32, rt: i32) -> i32 {
7264    hexagon_M2_mpysu_up(rs, rt)
7265}
7266
7267/// `Rx32+=mpyu(Rs32.h,Rt32.h)`
7268///
7269/// Instruction Type: M
7270/// Execution Slots: SLOT23
7271#[inline(always)]
7272#[cfg_attr(test, assert_instr(mpyu))]
7273#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7274pub unsafe fn Q6_R_mpyuacc_RhRh(rx: i32, rs: i32, rt: i32) -> i32 {
7275    hexagon_M2_mpyu_acc_hh_s0(rx, rs, rt)
7276}
7277
7278/// `Rx32+=mpyu(Rs32.h,Rt32.h):<<1`
7279///
7280/// Instruction Type: M
7281/// Execution Slots: SLOT23
7282#[inline(always)]
7283#[cfg_attr(test, assert_instr(mpyu))]
7284#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7285pub unsafe fn Q6_R_mpyuacc_RhRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
7286    hexagon_M2_mpyu_acc_hh_s1(rx, rs, rt)
7287}
7288
7289/// `Rx32+=mpyu(Rs32.h,Rt32.l)`
7290///
7291/// Instruction Type: M
7292/// Execution Slots: SLOT23
7293#[inline(always)]
7294#[cfg_attr(test, assert_instr(mpyu))]
7295#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7296pub unsafe fn Q6_R_mpyuacc_RhRl(rx: i32, rs: i32, rt: i32) -> i32 {
7297    hexagon_M2_mpyu_acc_hl_s0(rx, rs, rt)
7298}
7299
7300/// `Rx32+=mpyu(Rs32.h,Rt32.l):<<1`
7301///
7302/// Instruction Type: M
7303/// Execution Slots: SLOT23
7304#[inline(always)]
7305#[cfg_attr(test, assert_instr(mpyu))]
7306#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7307pub unsafe fn Q6_R_mpyuacc_RhRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
7308    hexagon_M2_mpyu_acc_hl_s1(rx, rs, rt)
7309}
7310
7311/// `Rx32+=mpyu(Rs32.l,Rt32.h)`
7312///
7313/// Instruction Type: M
7314/// Execution Slots: SLOT23
7315#[inline(always)]
7316#[cfg_attr(test, assert_instr(mpyu))]
7317#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7318pub unsafe fn Q6_R_mpyuacc_RlRh(rx: i32, rs: i32, rt: i32) -> i32 {
7319    hexagon_M2_mpyu_acc_lh_s0(rx, rs, rt)
7320}
7321
7322/// `Rx32+=mpyu(Rs32.l,Rt32.h):<<1`
7323///
7324/// Instruction Type: M
7325/// Execution Slots: SLOT23
7326#[inline(always)]
7327#[cfg_attr(test, assert_instr(mpyu))]
7328#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7329pub unsafe fn Q6_R_mpyuacc_RlRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
7330    hexagon_M2_mpyu_acc_lh_s1(rx, rs, rt)
7331}
7332
7333/// `Rx32+=mpyu(Rs32.l,Rt32.l)`
7334///
7335/// Instruction Type: M
7336/// Execution Slots: SLOT23
7337#[inline(always)]
7338#[cfg_attr(test, assert_instr(mpyu))]
7339#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7340pub unsafe fn Q6_R_mpyuacc_RlRl(rx: i32, rs: i32, rt: i32) -> i32 {
7341    hexagon_M2_mpyu_acc_ll_s0(rx, rs, rt)
7342}
7343
7344/// `Rx32+=mpyu(Rs32.l,Rt32.l):<<1`
7345///
7346/// Instruction Type: M
7347/// Execution Slots: SLOT23
7348#[inline(always)]
7349#[cfg_attr(test, assert_instr(mpyu))]
7350#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7351pub unsafe fn Q6_R_mpyuacc_RlRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
7352    hexagon_M2_mpyu_acc_ll_s1(rx, rs, rt)
7353}
7354
7355/// `Rd32=mpyu(Rs32.h,Rt32.h)`
7356///
7357/// Instruction Type: M
7358/// Execution Slots: SLOT23
7359#[inline(always)]
7360#[cfg_attr(test, assert_instr(mpyu))]
7361#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7362pub unsafe fn Q6_R_mpyu_RhRh(rs: i32, rt: i32) -> i32 {
7363    hexagon_M2_mpyu_hh_s0(rs, rt)
7364}
7365
7366/// `Rd32=mpyu(Rs32.h,Rt32.h):<<1`
7367///
7368/// Instruction Type: M
7369/// Execution Slots: SLOT23
7370#[inline(always)]
7371#[cfg_attr(test, assert_instr(mpyu))]
7372#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7373pub unsafe fn Q6_R_mpyu_RhRh_s1(rs: i32, rt: i32) -> i32 {
7374    hexagon_M2_mpyu_hh_s1(rs, rt)
7375}
7376
7377/// `Rd32=mpyu(Rs32.h,Rt32.l)`
7378///
7379/// Instruction Type: M
7380/// Execution Slots: SLOT23
7381#[inline(always)]
7382#[cfg_attr(test, assert_instr(mpyu))]
7383#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7384pub unsafe fn Q6_R_mpyu_RhRl(rs: i32, rt: i32) -> i32 {
7385    hexagon_M2_mpyu_hl_s0(rs, rt)
7386}
7387
7388/// `Rd32=mpyu(Rs32.h,Rt32.l):<<1`
7389///
7390/// Instruction Type: M
7391/// Execution Slots: SLOT23
7392#[inline(always)]
7393#[cfg_attr(test, assert_instr(mpyu))]
7394#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7395pub unsafe fn Q6_R_mpyu_RhRl_s1(rs: i32, rt: i32) -> i32 {
7396    hexagon_M2_mpyu_hl_s1(rs, rt)
7397}
7398
7399/// `Rd32=mpyu(Rs32.l,Rt32.h)`
7400///
7401/// Instruction Type: M
7402/// Execution Slots: SLOT23
7403#[inline(always)]
7404#[cfg_attr(test, assert_instr(mpyu))]
7405#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7406pub unsafe fn Q6_R_mpyu_RlRh(rs: i32, rt: i32) -> i32 {
7407    hexagon_M2_mpyu_lh_s0(rs, rt)
7408}
7409
7410/// `Rd32=mpyu(Rs32.l,Rt32.h):<<1`
7411///
7412/// Instruction Type: M
7413/// Execution Slots: SLOT23
7414#[inline(always)]
7415#[cfg_attr(test, assert_instr(mpyu))]
7416#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7417pub unsafe fn Q6_R_mpyu_RlRh_s1(rs: i32, rt: i32) -> i32 {
7418    hexagon_M2_mpyu_lh_s1(rs, rt)
7419}
7420
7421/// `Rd32=mpyu(Rs32.l,Rt32.l)`
7422///
7423/// Instruction Type: M
7424/// Execution Slots: SLOT23
7425#[inline(always)]
7426#[cfg_attr(test, assert_instr(mpyu))]
7427#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7428pub unsafe fn Q6_R_mpyu_RlRl(rs: i32, rt: i32) -> i32 {
7429    hexagon_M2_mpyu_ll_s0(rs, rt)
7430}
7431
7432/// `Rd32=mpyu(Rs32.l,Rt32.l):<<1`
7433///
7434/// Instruction Type: M
7435/// Execution Slots: SLOT23
7436#[inline(always)]
7437#[cfg_attr(test, assert_instr(mpyu))]
7438#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7439pub unsafe fn Q6_R_mpyu_RlRl_s1(rs: i32, rt: i32) -> i32 {
7440    hexagon_M2_mpyu_ll_s1(rs, rt)
7441}
7442
7443/// `Rx32-=mpyu(Rs32.h,Rt32.h)`
7444///
7445/// Instruction Type: M
7446/// Execution Slots: SLOT23
7447#[inline(always)]
7448#[cfg_attr(test, assert_instr(mpyu))]
7449#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7450pub unsafe fn Q6_R_mpyunac_RhRh(rx: i32, rs: i32, rt: i32) -> i32 {
7451    hexagon_M2_mpyu_nac_hh_s0(rx, rs, rt)
7452}
7453
7454/// `Rx32-=mpyu(Rs32.h,Rt32.h):<<1`
7455///
7456/// Instruction Type: M
7457/// Execution Slots: SLOT23
7458#[inline(always)]
7459#[cfg_attr(test, assert_instr(mpyu))]
7460#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7461pub unsafe fn Q6_R_mpyunac_RhRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
7462    hexagon_M2_mpyu_nac_hh_s1(rx, rs, rt)
7463}
7464
7465/// `Rx32-=mpyu(Rs32.h,Rt32.l)`
7466///
7467/// Instruction Type: M
7468/// Execution Slots: SLOT23
7469#[inline(always)]
7470#[cfg_attr(test, assert_instr(mpyu))]
7471#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7472pub unsafe fn Q6_R_mpyunac_RhRl(rx: i32, rs: i32, rt: i32) -> i32 {
7473    hexagon_M2_mpyu_nac_hl_s0(rx, rs, rt)
7474}
7475
7476/// `Rx32-=mpyu(Rs32.h,Rt32.l):<<1`
7477///
7478/// Instruction Type: M
7479/// Execution Slots: SLOT23
7480#[inline(always)]
7481#[cfg_attr(test, assert_instr(mpyu))]
7482#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7483pub unsafe fn Q6_R_mpyunac_RhRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
7484    hexagon_M2_mpyu_nac_hl_s1(rx, rs, rt)
7485}
7486
7487/// `Rx32-=mpyu(Rs32.l,Rt32.h)`
7488///
7489/// Instruction Type: M
7490/// Execution Slots: SLOT23
7491#[inline(always)]
7492#[cfg_attr(test, assert_instr(mpyu))]
7493#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7494pub unsafe fn Q6_R_mpyunac_RlRh(rx: i32, rs: i32, rt: i32) -> i32 {
7495    hexagon_M2_mpyu_nac_lh_s0(rx, rs, rt)
7496}
7497
7498/// `Rx32-=mpyu(Rs32.l,Rt32.h):<<1`
7499///
7500/// Instruction Type: M
7501/// Execution Slots: SLOT23
7502#[inline(always)]
7503#[cfg_attr(test, assert_instr(mpyu))]
7504#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7505pub unsafe fn Q6_R_mpyunac_RlRh_s1(rx: i32, rs: i32, rt: i32) -> i32 {
7506    hexagon_M2_mpyu_nac_lh_s1(rx, rs, rt)
7507}
7508
7509/// `Rx32-=mpyu(Rs32.l,Rt32.l)`
7510///
7511/// Instruction Type: M
7512/// Execution Slots: SLOT23
7513#[inline(always)]
7514#[cfg_attr(test, assert_instr(mpyu))]
7515#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7516pub unsafe fn Q6_R_mpyunac_RlRl(rx: i32, rs: i32, rt: i32) -> i32 {
7517    hexagon_M2_mpyu_nac_ll_s0(rx, rs, rt)
7518}
7519
7520/// `Rx32-=mpyu(Rs32.l,Rt32.l):<<1`
7521///
7522/// Instruction Type: M
7523/// Execution Slots: SLOT23
7524#[inline(always)]
7525#[cfg_attr(test, assert_instr(mpyu))]
7526#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7527pub unsafe fn Q6_R_mpyunac_RlRl_s1(rx: i32, rs: i32, rt: i32) -> i32 {
7528    hexagon_M2_mpyu_nac_ll_s1(rx, rs, rt)
7529}
7530
7531/// `Rd32=mpyu(Rs32,Rt32)`
7532///
7533/// Instruction Type: M
7534/// Execution Slots: SLOT23
7535#[inline(always)]
7536#[cfg_attr(test, assert_instr(mpyu))]
7537#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7538pub unsafe fn Q6_R_mpyu_RR(rs: i32, rt: i32) -> i32 {
7539    hexagon_M2_mpyu_up(rs, rt)
7540}
7541
7542/// `Rxx32+=mpyu(Rs32.h,Rt32.h)`
7543///
7544/// Instruction Type: M
7545/// Execution Slots: SLOT23
7546#[inline(always)]
7547#[cfg_attr(test, assert_instr(mpyu))]
7548#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7549pub unsafe fn Q6_P_mpyuacc_RhRh(rxx: i64, rs: i32, rt: i32) -> i64 {
7550    hexagon_M2_mpyud_acc_hh_s0(rxx, rs, rt)
7551}
7552
7553/// `Rxx32+=mpyu(Rs32.h,Rt32.h):<<1`
7554///
7555/// Instruction Type: M
7556/// Execution Slots: SLOT23
7557#[inline(always)]
7558#[cfg_attr(test, assert_instr(mpyu))]
7559#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7560pub unsafe fn Q6_P_mpyuacc_RhRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7561    hexagon_M2_mpyud_acc_hh_s1(rxx, rs, rt)
7562}
7563
7564/// `Rxx32+=mpyu(Rs32.h,Rt32.l)`
7565///
7566/// Instruction Type: M
7567/// Execution Slots: SLOT23
7568#[inline(always)]
7569#[cfg_attr(test, assert_instr(mpyu))]
7570#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7571pub unsafe fn Q6_P_mpyuacc_RhRl(rxx: i64, rs: i32, rt: i32) -> i64 {
7572    hexagon_M2_mpyud_acc_hl_s0(rxx, rs, rt)
7573}
7574
7575/// `Rxx32+=mpyu(Rs32.h,Rt32.l):<<1`
7576///
7577/// Instruction Type: M
7578/// Execution Slots: SLOT23
7579#[inline(always)]
7580#[cfg_attr(test, assert_instr(mpyu))]
7581#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7582pub unsafe fn Q6_P_mpyuacc_RhRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7583    hexagon_M2_mpyud_acc_hl_s1(rxx, rs, rt)
7584}
7585
7586/// `Rxx32+=mpyu(Rs32.l,Rt32.h)`
7587///
7588/// Instruction Type: M
7589/// Execution Slots: SLOT23
7590#[inline(always)]
7591#[cfg_attr(test, assert_instr(mpyu))]
7592#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7593pub unsafe fn Q6_P_mpyuacc_RlRh(rxx: i64, rs: i32, rt: i32) -> i64 {
7594    hexagon_M2_mpyud_acc_lh_s0(rxx, rs, rt)
7595}
7596
7597/// `Rxx32+=mpyu(Rs32.l,Rt32.h):<<1`
7598///
7599/// Instruction Type: M
7600/// Execution Slots: SLOT23
7601#[inline(always)]
7602#[cfg_attr(test, assert_instr(mpyu))]
7603#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7604pub unsafe fn Q6_P_mpyuacc_RlRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7605    hexagon_M2_mpyud_acc_lh_s1(rxx, rs, rt)
7606}
7607
7608/// `Rxx32+=mpyu(Rs32.l,Rt32.l)`
7609///
7610/// Instruction Type: M
7611/// Execution Slots: SLOT23
7612#[inline(always)]
7613#[cfg_attr(test, assert_instr(mpyu))]
7614#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7615pub unsafe fn Q6_P_mpyuacc_RlRl(rxx: i64, rs: i32, rt: i32) -> i64 {
7616    hexagon_M2_mpyud_acc_ll_s0(rxx, rs, rt)
7617}
7618
7619/// `Rxx32+=mpyu(Rs32.l,Rt32.l):<<1`
7620///
7621/// Instruction Type: M
7622/// Execution Slots: SLOT23
7623#[inline(always)]
7624#[cfg_attr(test, assert_instr(mpyu))]
7625#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7626pub unsafe fn Q6_P_mpyuacc_RlRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7627    hexagon_M2_mpyud_acc_ll_s1(rxx, rs, rt)
7628}
7629
7630/// `Rdd32=mpyu(Rs32.h,Rt32.h)`
7631///
7632/// Instruction Type: M
7633/// Execution Slots: SLOT23
7634#[inline(always)]
7635#[cfg_attr(test, assert_instr(mpyu))]
7636#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7637pub unsafe fn Q6_P_mpyu_RhRh(rs: i32, rt: i32) -> i64 {
7638    hexagon_M2_mpyud_hh_s0(rs, rt)
7639}
7640
7641/// `Rdd32=mpyu(Rs32.h,Rt32.h):<<1`
7642///
7643/// Instruction Type: M
7644/// Execution Slots: SLOT23
7645#[inline(always)]
7646#[cfg_attr(test, assert_instr(mpyu))]
7647#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7648pub unsafe fn Q6_P_mpyu_RhRh_s1(rs: i32, rt: i32) -> i64 {
7649    hexagon_M2_mpyud_hh_s1(rs, rt)
7650}
7651
7652/// `Rdd32=mpyu(Rs32.h,Rt32.l)`
7653///
7654/// Instruction Type: M
7655/// Execution Slots: SLOT23
7656#[inline(always)]
7657#[cfg_attr(test, assert_instr(mpyu))]
7658#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7659pub unsafe fn Q6_P_mpyu_RhRl(rs: i32, rt: i32) -> i64 {
7660    hexagon_M2_mpyud_hl_s0(rs, rt)
7661}
7662
7663/// `Rdd32=mpyu(Rs32.h,Rt32.l):<<1`
7664///
7665/// Instruction Type: M
7666/// Execution Slots: SLOT23
7667#[inline(always)]
7668#[cfg_attr(test, assert_instr(mpyu))]
7669#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7670pub unsafe fn Q6_P_mpyu_RhRl_s1(rs: i32, rt: i32) -> i64 {
7671    hexagon_M2_mpyud_hl_s1(rs, rt)
7672}
7673
7674/// `Rdd32=mpyu(Rs32.l,Rt32.h)`
7675///
7676/// Instruction Type: M
7677/// Execution Slots: SLOT23
7678#[inline(always)]
7679#[cfg_attr(test, assert_instr(mpyu))]
7680#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7681pub unsafe fn Q6_P_mpyu_RlRh(rs: i32, rt: i32) -> i64 {
7682    hexagon_M2_mpyud_lh_s0(rs, rt)
7683}
7684
7685/// `Rdd32=mpyu(Rs32.l,Rt32.h):<<1`
7686///
7687/// Instruction Type: M
7688/// Execution Slots: SLOT23
7689#[inline(always)]
7690#[cfg_attr(test, assert_instr(mpyu))]
7691#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7692pub unsafe fn Q6_P_mpyu_RlRh_s1(rs: i32, rt: i32) -> i64 {
7693    hexagon_M2_mpyud_lh_s1(rs, rt)
7694}
7695
7696/// `Rdd32=mpyu(Rs32.l,Rt32.l)`
7697///
7698/// Instruction Type: M
7699/// Execution Slots: SLOT23
7700#[inline(always)]
7701#[cfg_attr(test, assert_instr(mpyu))]
7702#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7703pub unsafe fn Q6_P_mpyu_RlRl(rs: i32, rt: i32) -> i64 {
7704    hexagon_M2_mpyud_ll_s0(rs, rt)
7705}
7706
7707/// `Rdd32=mpyu(Rs32.l,Rt32.l):<<1`
7708///
7709/// Instruction Type: M
7710/// Execution Slots: SLOT23
7711#[inline(always)]
7712#[cfg_attr(test, assert_instr(mpyu))]
7713#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7714pub unsafe fn Q6_P_mpyu_RlRl_s1(rs: i32, rt: i32) -> i64 {
7715    hexagon_M2_mpyud_ll_s1(rs, rt)
7716}
7717
7718/// `Rxx32-=mpyu(Rs32.h,Rt32.h)`
7719///
7720/// Instruction Type: M
7721/// Execution Slots: SLOT23
7722#[inline(always)]
7723#[cfg_attr(test, assert_instr(mpyu))]
7724#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7725pub unsafe fn Q6_P_mpyunac_RhRh(rxx: i64, rs: i32, rt: i32) -> i64 {
7726    hexagon_M2_mpyud_nac_hh_s0(rxx, rs, rt)
7727}
7728
7729/// `Rxx32-=mpyu(Rs32.h,Rt32.h):<<1`
7730///
7731/// Instruction Type: M
7732/// Execution Slots: SLOT23
7733#[inline(always)]
7734#[cfg_attr(test, assert_instr(mpyu))]
7735#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7736pub unsafe fn Q6_P_mpyunac_RhRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7737    hexagon_M2_mpyud_nac_hh_s1(rxx, rs, rt)
7738}
7739
7740/// `Rxx32-=mpyu(Rs32.h,Rt32.l)`
7741///
7742/// Instruction Type: M
7743/// Execution Slots: SLOT23
7744#[inline(always)]
7745#[cfg_attr(test, assert_instr(mpyu))]
7746#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7747pub unsafe fn Q6_P_mpyunac_RhRl(rxx: i64, rs: i32, rt: i32) -> i64 {
7748    hexagon_M2_mpyud_nac_hl_s0(rxx, rs, rt)
7749}
7750
7751/// `Rxx32-=mpyu(Rs32.h,Rt32.l):<<1`
7752///
7753/// Instruction Type: M
7754/// Execution Slots: SLOT23
7755#[inline(always)]
7756#[cfg_attr(test, assert_instr(mpyu))]
7757#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7758pub unsafe fn Q6_P_mpyunac_RhRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7759    hexagon_M2_mpyud_nac_hl_s1(rxx, rs, rt)
7760}
7761
7762/// `Rxx32-=mpyu(Rs32.l,Rt32.h)`
7763///
7764/// Instruction Type: M
7765/// Execution Slots: SLOT23
7766#[inline(always)]
7767#[cfg_attr(test, assert_instr(mpyu))]
7768#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7769pub unsafe fn Q6_P_mpyunac_RlRh(rxx: i64, rs: i32, rt: i32) -> i64 {
7770    hexagon_M2_mpyud_nac_lh_s0(rxx, rs, rt)
7771}
7772
7773/// `Rxx32-=mpyu(Rs32.l,Rt32.h):<<1`
7774///
7775/// Instruction Type: M
7776/// Execution Slots: SLOT23
7777#[inline(always)]
7778#[cfg_attr(test, assert_instr(mpyu))]
7779#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7780pub unsafe fn Q6_P_mpyunac_RlRh_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7781    hexagon_M2_mpyud_nac_lh_s1(rxx, rs, rt)
7782}
7783
7784/// `Rxx32-=mpyu(Rs32.l,Rt32.l)`
7785///
7786/// Instruction Type: M
7787/// Execution Slots: SLOT23
7788#[inline(always)]
7789#[cfg_attr(test, assert_instr(mpyu))]
7790#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7791pub unsafe fn Q6_P_mpyunac_RlRl(rxx: i64, rs: i32, rt: i32) -> i64 {
7792    hexagon_M2_mpyud_nac_ll_s0(rxx, rs, rt)
7793}
7794
7795/// `Rxx32-=mpyu(Rs32.l,Rt32.l):<<1`
7796///
7797/// Instruction Type: M
7798/// Execution Slots: SLOT23
7799#[inline(always)]
7800#[cfg_attr(test, assert_instr(mpyu))]
7801#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7802pub unsafe fn Q6_P_mpyunac_RlRl_s1(rxx: i64, rs: i32, rt: i32) -> i64 {
7803    hexagon_M2_mpyud_nac_ll_s1(rxx, rs, rt)
7804}
7805
7806/// `Rd32=mpyui(Rs32,Rt32)`
7807///
7808/// Instruction Type: M
7809/// Execution Slots: SLOT0123
7810#[inline(always)]
7811#[cfg_attr(test, assert_instr(mpyui))]
7812#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7813pub unsafe fn Q6_R_mpyui_RR(rs: i32, rt: i32) -> i32 {
7814    hexagon_M2_mpyui(rs, rt)
7815}
7816
7817/// `Rx32-=add(Rs32,Rt32)`
7818///
7819/// Instruction Type: M
7820/// Execution Slots: SLOT23
7821#[inline(always)]
7822#[cfg_attr(test, assert_instr(add))]
7823#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7824pub unsafe fn Q6_R_addnac_RR(rx: i32, rs: i32, rt: i32) -> i32 {
7825    hexagon_M2_nacci(rx, rs, rt)
7826}
7827
7828/// `Rx32-=add(Rs32,#s8)`
7829///
7830/// Instruction Type: M
7831/// Execution Slots: SLOT23
7832#[inline(always)]
7833#[rustc_legacy_const_generics(2)]
7834#[cfg_attr(test, assert_instr(add, IS8 = 0))]
7835#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7836pub unsafe fn Q6_R_addnac_RI<const IS8: i32>(rx: i32, rs: i32) -> i32 {
7837    static_assert_simm_bits!(IS8, 8);
7838    hexagon_M2_naccii(rx, rs, IS8)
7839}
7840
7841/// `Rx32+=sub(Rt32,Rs32)`
7842///
7843/// Instruction Type: M
7844/// Execution Slots: SLOT23
7845#[inline(always)]
7846#[cfg_attr(test, assert_instr(sub))]
7847#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7848pub unsafe fn Q6_R_subacc_RR(rx: i32, rt: i32, rs: i32) -> i32 {
7849    hexagon_M2_subacc(rx, rt, rs)
7850}
7851
7852/// `Rdd32=vabsdiffh(Rtt32,Rss32)`
7853///
7854/// Instruction Type: M
7855/// Execution Slots: SLOT23
7856#[inline(always)]
7857#[cfg_attr(test, assert_instr(vabsdiffh))]
7858#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7859pub unsafe fn Q6_P_vabsdiffh_PP(rtt: i64, rss: i64) -> i64 {
7860    hexagon_M2_vabsdiffh(rtt, rss)
7861}
7862
7863/// `Rdd32=vabsdiffw(Rtt32,Rss32)`
7864///
7865/// Instruction Type: M
7866/// Execution Slots: SLOT23
7867#[inline(always)]
7868#[cfg_attr(test, assert_instr(vabsdiffw))]
7869#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7870pub unsafe fn Q6_P_vabsdiffw_PP(rtt: i64, rss: i64) -> i64 {
7871    hexagon_M2_vabsdiffw(rtt, rss)
7872}
7873
7874/// `Rxx32+=vcmpyi(Rss32,Rtt32):sat`
7875///
7876/// Instruction Type: M
7877/// Execution Slots: SLOT23
7878#[inline(always)]
7879#[cfg_attr(test, assert_instr(vcmpyi))]
7880#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7881pub unsafe fn Q6_P_vcmpyiacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
7882    hexagon_M2_vcmac_s0_sat_i(rxx, rss, rtt)
7883}
7884
7885/// `Rxx32+=vcmpyr(Rss32,Rtt32):sat`
7886///
7887/// Instruction Type: M
7888/// Execution Slots: SLOT23
7889#[inline(always)]
7890#[cfg_attr(test, assert_instr(vcmpyr))]
7891#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7892pub unsafe fn Q6_P_vcmpyracc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
7893    hexagon_M2_vcmac_s0_sat_r(rxx, rss, rtt)
7894}
7895
7896/// `Rdd32=vcmpyi(Rss32,Rtt32):sat`
7897///
7898/// Instruction Type: M
7899/// Execution Slots: SLOT23
7900#[inline(always)]
7901#[cfg_attr(test, assert_instr(vcmpyi))]
7902#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7903pub unsafe fn Q6_P_vcmpyi_PP_sat(rss: i64, rtt: i64) -> i64 {
7904    hexagon_M2_vcmpy_s0_sat_i(rss, rtt)
7905}
7906
7907/// `Rdd32=vcmpyr(Rss32,Rtt32):sat`
7908///
7909/// Instruction Type: M
7910/// Execution Slots: SLOT23
7911#[inline(always)]
7912#[cfg_attr(test, assert_instr(vcmpyr))]
7913#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7914pub unsafe fn Q6_P_vcmpyr_PP_sat(rss: i64, rtt: i64) -> i64 {
7915    hexagon_M2_vcmpy_s0_sat_r(rss, rtt)
7916}
7917
7918/// `Rdd32=vcmpyi(Rss32,Rtt32):<<1:sat`
7919///
7920/// Instruction Type: M
7921/// Execution Slots: SLOT23
7922#[inline(always)]
7923#[cfg_attr(test, assert_instr(vcmpyi))]
7924#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7925pub unsafe fn Q6_P_vcmpyi_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
7926    hexagon_M2_vcmpy_s1_sat_i(rss, rtt)
7927}
7928
7929/// `Rdd32=vcmpyr(Rss32,Rtt32):<<1:sat`
7930///
7931/// Instruction Type: M
7932/// Execution Slots: SLOT23
7933#[inline(always)]
7934#[cfg_attr(test, assert_instr(vcmpyr))]
7935#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7936pub unsafe fn Q6_P_vcmpyr_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
7937    hexagon_M2_vcmpy_s1_sat_r(rss, rtt)
7938}
7939
7940/// `Rxx32+=vdmpy(Rss32,Rtt32):sat`
7941///
7942/// Instruction Type: M
7943/// Execution Slots: SLOT23
7944#[inline(always)]
7945#[cfg_attr(test, assert_instr(vdmpy))]
7946#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7947pub unsafe fn Q6_P_vdmpyacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
7948    hexagon_M2_vdmacs_s0(rxx, rss, rtt)
7949}
7950
7951/// `Rxx32+=vdmpy(Rss32,Rtt32):<<1:sat`
7952///
7953/// Instruction Type: M
7954/// Execution Slots: SLOT23
7955#[inline(always)]
7956#[cfg_attr(test, assert_instr(vdmpy))]
7957#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7958pub unsafe fn Q6_P_vdmpyacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
7959    hexagon_M2_vdmacs_s1(rxx, rss, rtt)
7960}
7961
7962/// `Rd32=vdmpy(Rss32,Rtt32):rnd:sat`
7963///
7964/// Instruction Type: M
7965/// Execution Slots: SLOT23
7966#[inline(always)]
7967#[cfg_attr(test, assert_instr(vdmpy))]
7968#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7969pub unsafe fn Q6_R_vdmpy_PP_rnd_sat(rss: i64, rtt: i64) -> i32 {
7970    hexagon_M2_vdmpyrs_s0(rss, rtt)
7971}
7972
7973/// `Rd32=vdmpy(Rss32,Rtt32):<<1:rnd:sat`
7974///
7975/// Instruction Type: M
7976/// Execution Slots: SLOT23
7977#[inline(always)]
7978#[cfg_attr(test, assert_instr(vdmpy))]
7979#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7980pub unsafe fn Q6_R_vdmpy_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i32 {
7981    hexagon_M2_vdmpyrs_s1(rss, rtt)
7982}
7983
7984/// `Rdd32=vdmpy(Rss32,Rtt32):sat`
7985///
7986/// Instruction Type: M
7987/// Execution Slots: SLOT23
7988#[inline(always)]
7989#[cfg_attr(test, assert_instr(vdmpy))]
7990#[unstable(feature = "stdarch_hexagon", issue = "151523")]
7991pub unsafe fn Q6_P_vdmpy_PP_sat(rss: i64, rtt: i64) -> i64 {
7992    hexagon_M2_vdmpys_s0(rss, rtt)
7993}
7994
7995/// `Rdd32=vdmpy(Rss32,Rtt32):<<1:sat`
7996///
7997/// Instruction Type: M
7998/// Execution Slots: SLOT23
7999#[inline(always)]
8000#[cfg_attr(test, assert_instr(vdmpy))]
8001#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8002pub unsafe fn Q6_P_vdmpy_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
8003    hexagon_M2_vdmpys_s1(rss, rtt)
8004}
8005
8006/// `Rxx32+=vmpyh(Rs32,Rt32)`
8007///
8008/// Instruction Type: M
8009/// Execution Slots: SLOT23
8010#[inline(always)]
8011#[cfg_attr(test, assert_instr(vmpyh))]
8012#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8013pub unsafe fn Q6_P_vmpyhacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
8014    hexagon_M2_vmac2(rxx, rs, rt)
8015}
8016
8017/// `Rxx32+=vmpyeh(Rss32,Rtt32)`
8018///
8019/// Instruction Type: M
8020/// Execution Slots: SLOT23
8021#[inline(always)]
8022#[cfg_attr(test, assert_instr(vmpyeh))]
8023#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8024pub unsafe fn Q6_P_vmpyehacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
8025    hexagon_M2_vmac2es(rxx, rss, rtt)
8026}
8027
8028/// `Rxx32+=vmpyeh(Rss32,Rtt32):sat`
8029///
8030/// Instruction Type: M
8031/// Execution Slots: SLOT23
8032#[inline(always)]
8033#[cfg_attr(test, assert_instr(vmpyeh))]
8034#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8035pub unsafe fn Q6_P_vmpyehacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
8036    hexagon_M2_vmac2es_s0(rxx, rss, rtt)
8037}
8038
8039/// `Rxx32+=vmpyeh(Rss32,Rtt32):<<1:sat`
8040///
8041/// Instruction Type: M
8042/// Execution Slots: SLOT23
8043#[inline(always)]
8044#[cfg_attr(test, assert_instr(vmpyeh))]
8045#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8046pub unsafe fn Q6_P_vmpyehacc_PP_s1_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
8047    hexagon_M2_vmac2es_s1(rxx, rss, rtt)
8048}
8049
8050/// `Rxx32+=vmpyh(Rs32,Rt32):sat`
8051///
8052/// Instruction Type: M
8053/// Execution Slots: SLOT23
8054#[inline(always)]
8055#[cfg_attr(test, assert_instr(vmpyh))]
8056#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8057pub unsafe fn Q6_P_vmpyhacc_RR_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
8058    hexagon_M2_vmac2s_s0(rxx, rs, rt)
8059}
8060
8061/// `Rxx32+=vmpyh(Rs32,Rt32):<<1:sat`
8062///
8063/// Instruction Type: M
8064/// Execution Slots: SLOT23
8065#[inline(always)]
8066#[cfg_attr(test, assert_instr(vmpyh))]
8067#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8068pub unsafe fn Q6_P_vmpyhacc_RR_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
8069    hexagon_M2_vmac2s_s1(rxx, rs, rt)
8070}
8071
8072/// `Rxx32+=vmpyhsu(Rs32,Rt32):sat`
8073///
8074/// Instruction Type: M
8075/// Execution Slots: SLOT23
8076#[inline(always)]
8077#[cfg_attr(test, assert_instr(vmpyhsu))]
8078#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8079pub unsafe fn Q6_P_vmpyhsuacc_RR_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
8080    hexagon_M2_vmac2su_s0(rxx, rs, rt)
8081}
8082
8083/// `Rxx32+=vmpyhsu(Rs32,Rt32):<<1:sat`
8084///
8085/// Instruction Type: M
8086/// Execution Slots: SLOT23
8087#[inline(always)]
8088#[cfg_attr(test, assert_instr(vmpyhsu))]
8089#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8090pub unsafe fn Q6_P_vmpyhsuacc_RR_s1_sat(rxx: i64, rs: i32, rt: i32) -> i64 {
8091    hexagon_M2_vmac2su_s1(rxx, rs, rt)
8092}
8093
8094/// `Rdd32=vmpyeh(Rss32,Rtt32):sat`
8095///
8096/// Instruction Type: M
8097/// Execution Slots: SLOT23
8098#[inline(always)]
8099#[cfg_attr(test, assert_instr(vmpyeh))]
8100#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8101pub unsafe fn Q6_P_vmpyeh_PP_sat(rss: i64, rtt: i64) -> i64 {
8102    hexagon_M2_vmpy2es_s0(rss, rtt)
8103}
8104
8105/// `Rdd32=vmpyeh(Rss32,Rtt32):<<1:sat`
8106///
8107/// Instruction Type: M
8108/// Execution Slots: SLOT23
8109#[inline(always)]
8110#[cfg_attr(test, assert_instr(vmpyeh))]
8111#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8112pub unsafe fn Q6_P_vmpyeh_PP_s1_sat(rss: i64, rtt: i64) -> i64 {
8113    hexagon_M2_vmpy2es_s1(rss, rtt)
8114}
8115
8116/// `Rdd32=vmpyh(Rs32,Rt32):sat`
8117///
8118/// Instruction Type: M
8119/// Execution Slots: SLOT23
8120#[inline(always)]
8121#[cfg_attr(test, assert_instr(vmpyh))]
8122#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8123pub unsafe fn Q6_P_vmpyh_RR_sat(rs: i32, rt: i32) -> i64 {
8124    hexagon_M2_vmpy2s_s0(rs, rt)
8125}
8126
8127/// `Rd32=vmpyh(Rs32,Rt32):rnd:sat`
8128///
8129/// Instruction Type: M
8130/// Execution Slots: SLOT23
8131#[inline(always)]
8132#[cfg_attr(test, assert_instr(vmpyh))]
8133#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8134pub unsafe fn Q6_R_vmpyh_RR_rnd_sat(rs: i32, rt: i32) -> i32 {
8135    hexagon_M2_vmpy2s_s0pack(rs, rt)
8136}
8137
8138/// `Rdd32=vmpyh(Rs32,Rt32):<<1:sat`
8139///
8140/// Instruction Type: M
8141/// Execution Slots: SLOT23
8142#[inline(always)]
8143#[cfg_attr(test, assert_instr(vmpyh))]
8144#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8145pub unsafe fn Q6_P_vmpyh_RR_s1_sat(rs: i32, rt: i32) -> i64 {
8146    hexagon_M2_vmpy2s_s1(rs, rt)
8147}
8148
8149/// `Rd32=vmpyh(Rs32,Rt32):<<1:rnd:sat`
8150///
8151/// Instruction Type: M
8152/// Execution Slots: SLOT23
8153#[inline(always)]
8154#[cfg_attr(test, assert_instr(vmpyh))]
8155#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8156pub unsafe fn Q6_R_vmpyh_RR_s1_rnd_sat(rs: i32, rt: i32) -> i32 {
8157    hexagon_M2_vmpy2s_s1pack(rs, rt)
8158}
8159
8160/// `Rdd32=vmpyhsu(Rs32,Rt32):sat`
8161///
8162/// Instruction Type: M
8163/// Execution Slots: SLOT23
8164#[inline(always)]
8165#[cfg_attr(test, assert_instr(vmpyhsu))]
8166#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8167pub unsafe fn Q6_P_vmpyhsu_RR_sat(rs: i32, rt: i32) -> i64 {
8168    hexagon_M2_vmpy2su_s0(rs, rt)
8169}
8170
8171/// `Rdd32=vmpyhsu(Rs32,Rt32):<<1:sat`
8172///
8173/// Instruction Type: M
8174/// Execution Slots: SLOT23
8175#[inline(always)]
8176#[cfg_attr(test, assert_instr(vmpyhsu))]
8177#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8178pub unsafe fn Q6_P_vmpyhsu_RR_s1_sat(rs: i32, rt: i32) -> i64 {
8179    hexagon_M2_vmpy2su_s1(rs, rt)
8180}
8181
8182/// `Rd32=vraddh(Rss32,Rtt32)`
8183///
8184/// Instruction Type: M
8185/// Execution Slots: SLOT23
8186#[inline(always)]
8187#[cfg_attr(test, assert_instr(vraddh))]
8188#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8189pub unsafe fn Q6_R_vraddh_PP(rss: i64, rtt: i64) -> i32 {
8190    hexagon_M2_vraddh(rss, rtt)
8191}
8192
8193/// `Rd32=vradduh(Rss32,Rtt32)`
8194///
8195/// Instruction Type: M
8196/// Execution Slots: SLOT23
8197#[inline(always)]
8198#[cfg_attr(test, assert_instr(vradduh))]
8199#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8200pub unsafe fn Q6_R_vradduh_PP(rss: i64, rtt: i64) -> i32 {
8201    hexagon_M2_vradduh(rss, rtt)
8202}
8203
8204/// `Rxx32+=vrcmpyi(Rss32,Rtt32)`
8205///
8206/// Instruction Type: M
8207/// Execution Slots: SLOT23
8208#[inline(always)]
8209#[cfg_attr(test, assert_instr(vrcmpyi))]
8210#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8211pub unsafe fn Q6_P_vrcmpyiacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
8212    hexagon_M2_vrcmaci_s0(rxx, rss, rtt)
8213}
8214
8215/// `Rxx32+=vrcmpyi(Rss32,Rtt32*)`
8216///
8217/// Instruction Type: M
8218/// Execution Slots: SLOT23
8219#[inline(always)]
8220#[cfg_attr(test, assert_instr(vrcmpyi))]
8221#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8222pub unsafe fn Q6_P_vrcmpyiacc_PP_conj(rxx: i64, rss: i64, rtt: i64) -> i64 {
8223    hexagon_M2_vrcmaci_s0c(rxx, rss, rtt)
8224}
8225
8226/// `Rxx32+=vrcmpyr(Rss32,Rtt32)`
8227///
8228/// Instruction Type: M
8229/// Execution Slots: SLOT23
8230#[inline(always)]
8231#[cfg_attr(test, assert_instr(vrcmpyr))]
8232#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8233pub unsafe fn Q6_P_vrcmpyracc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
8234    hexagon_M2_vrcmacr_s0(rxx, rss, rtt)
8235}
8236
8237/// `Rxx32+=vrcmpyr(Rss32,Rtt32*)`
8238///
8239/// Instruction Type: M
8240/// Execution Slots: SLOT23
8241#[inline(always)]
8242#[cfg_attr(test, assert_instr(vrcmpyr))]
8243#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8244pub unsafe fn Q6_P_vrcmpyracc_PP_conj(rxx: i64, rss: i64, rtt: i64) -> i64 {
8245    hexagon_M2_vrcmacr_s0c(rxx, rss, rtt)
8246}
8247
8248/// `Rdd32=vrcmpyi(Rss32,Rtt32)`
8249///
8250/// Instruction Type: M
8251/// Execution Slots: SLOT23
8252#[inline(always)]
8253#[cfg_attr(test, assert_instr(vrcmpyi))]
8254#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8255pub unsafe fn Q6_P_vrcmpyi_PP(rss: i64, rtt: i64) -> i64 {
8256    hexagon_M2_vrcmpyi_s0(rss, rtt)
8257}
8258
8259/// `Rdd32=vrcmpyi(Rss32,Rtt32*)`
8260///
8261/// Instruction Type: M
8262/// Execution Slots: SLOT23
8263#[inline(always)]
8264#[cfg_attr(test, assert_instr(vrcmpyi))]
8265#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8266pub unsafe fn Q6_P_vrcmpyi_PP_conj(rss: i64, rtt: i64) -> i64 {
8267    hexagon_M2_vrcmpyi_s0c(rss, rtt)
8268}
8269
8270/// `Rdd32=vrcmpyr(Rss32,Rtt32)`
8271///
8272/// Instruction Type: M
8273/// Execution Slots: SLOT23
8274#[inline(always)]
8275#[cfg_attr(test, assert_instr(vrcmpyr))]
8276#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8277pub unsafe fn Q6_P_vrcmpyr_PP(rss: i64, rtt: i64) -> i64 {
8278    hexagon_M2_vrcmpyr_s0(rss, rtt)
8279}
8280
8281/// `Rdd32=vrcmpyr(Rss32,Rtt32*)`
8282///
8283/// Instruction Type: M
8284/// Execution Slots: SLOT23
8285#[inline(always)]
8286#[cfg_attr(test, assert_instr(vrcmpyr))]
8287#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8288pub unsafe fn Q6_P_vrcmpyr_PP_conj(rss: i64, rtt: i64) -> i64 {
8289    hexagon_M2_vrcmpyr_s0c(rss, rtt)
8290}
8291
8292/// `Rxx32+=vrcmpys(Rss32,Rt32):<<1:sat`
8293///
8294/// Instruction Type: M
8295/// Execution Slots: SLOT0123
8296#[inline(always)]
8297#[cfg_attr(test, assert_instr(vrcmpys))]
8298#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8299pub unsafe fn Q6_P_vrcmpysacc_PR_s1_sat(rxx: i64, rss: i64, rt: i32) -> i64 {
8300    hexagon_M2_vrcmpys_acc_s1(rxx, rss, rt)
8301}
8302
8303/// `Rdd32=vrcmpys(Rss32,Rt32):<<1:sat`
8304///
8305/// Instruction Type: M
8306/// Execution Slots: SLOT0123
8307#[inline(always)]
8308#[cfg_attr(test, assert_instr(vrcmpys))]
8309#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8310pub unsafe fn Q6_P_vrcmpys_PR_s1_sat(rss: i64, rt: i32) -> i64 {
8311    hexagon_M2_vrcmpys_s1(rss, rt)
8312}
8313
8314/// `Rd32=vrcmpys(Rss32,Rt32):<<1:rnd:sat`
8315///
8316/// Instruction Type: M
8317/// Execution Slots: SLOT0123
8318#[inline(always)]
8319#[cfg_attr(test, assert_instr(vrcmpys))]
8320#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8321pub unsafe fn Q6_R_vrcmpys_PR_s1_rnd_sat(rss: i64, rt: i32) -> i32 {
8322    hexagon_M2_vrcmpys_s1rp(rss, rt)
8323}
8324
8325/// `Rxx32+=vrmpyh(Rss32,Rtt32)`
8326///
8327/// Instruction Type: M
8328/// Execution Slots: SLOT23
8329#[inline(always)]
8330#[cfg_attr(test, assert_instr(vrmpyh))]
8331#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8332pub unsafe fn Q6_P_vrmpyhacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
8333    hexagon_M2_vrmac_s0(rxx, rss, rtt)
8334}
8335
8336/// `Rdd32=vrmpyh(Rss32,Rtt32)`
8337///
8338/// Instruction Type: M
8339/// Execution Slots: SLOT23
8340#[inline(always)]
8341#[cfg_attr(test, assert_instr(vrmpyh))]
8342#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8343pub unsafe fn Q6_P_vrmpyh_PP(rss: i64, rtt: i64) -> i64 {
8344    hexagon_M2_vrmpy_s0(rss, rtt)
8345}
8346
8347/// `Rx32^=xor(Rs32,Rt32)`
8348///
8349/// Instruction Type: M
8350/// Execution Slots: SLOT23
8351#[inline(always)]
8352#[cfg_attr(test, assert_instr(xor))]
8353#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8354pub unsafe fn Q6_R_xorxacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
8355    hexagon_M2_xor_xacc(rx, rs, rt)
8356}
8357
8358/// `Rx32&=and(Rs32,Rt32)`
8359///
8360/// Instruction Type: M
8361/// Execution Slots: SLOT23
8362#[inline(always)]
8363#[cfg_attr(test, assert_instr(and))]
8364#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8365pub unsafe fn Q6_R_andand_RR(rx: i32, rs: i32, rt: i32) -> i32 {
8366    hexagon_M4_and_and(rx, rs, rt)
8367}
8368
8369/// `Rx32&=and(Rs32,~Rt32)`
8370///
8371/// Instruction Type: M
8372/// Execution Slots: SLOT23
8373#[inline(always)]
8374#[cfg_attr(test, assert_instr(and))]
8375#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8376pub unsafe fn Q6_R_andand_RnR(rx: i32, rs: i32, rt: i32) -> i32 {
8377    hexagon_M4_and_andn(rx, rs, rt)
8378}
8379
8380/// `Rx32&=or(Rs32,Rt32)`
8381///
8382/// Instruction Type: M
8383/// Execution Slots: SLOT23
8384#[inline(always)]
8385#[cfg_attr(test, assert_instr(or))]
8386#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8387pub unsafe fn Q6_R_orand_RR(rx: i32, rs: i32, rt: i32) -> i32 {
8388    hexagon_M4_and_or(rx, rs, rt)
8389}
8390
8391/// `Rx32&=xor(Rs32,Rt32)`
8392///
8393/// Instruction Type: M
8394/// Execution Slots: SLOT23
8395#[inline(always)]
8396#[cfg_attr(test, assert_instr(xor))]
8397#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8398pub unsafe fn Q6_R_xorand_RR(rx: i32, rs: i32, rt: i32) -> i32 {
8399    hexagon_M4_and_xor(rx, rs, rt)
8400}
8401
8402/// `Rd32=cmpyiwh(Rss32,Rt32):<<1:rnd:sat`
8403///
8404/// Instruction Type: S_3op
8405/// Execution Slots: SLOT23
8406#[inline(always)]
8407#[cfg_attr(test, assert_instr(cmpyiwh))]
8408#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8409pub unsafe fn Q6_R_cmpyiwh_PR_s1_rnd_sat(rss: i64, rt: i32) -> i32 {
8410    hexagon_M4_cmpyi_wh(rss, rt)
8411}
8412
8413/// `Rd32=cmpyiwh(Rss32,Rt32*):<<1:rnd:sat`
8414///
8415/// Instruction Type: S_3op
8416/// Execution Slots: SLOT23
8417#[inline(always)]
8418#[cfg_attr(test, assert_instr(cmpyiwh))]
8419#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8420pub unsafe fn Q6_R_cmpyiwh_PR_conj_s1_rnd_sat(rss: i64, rt: i32) -> i32 {
8421    hexagon_M4_cmpyi_whc(rss, rt)
8422}
8423
8424/// `Rd32=cmpyrwh(Rss32,Rt32):<<1:rnd:sat`
8425///
8426/// Instruction Type: S_3op
8427/// Execution Slots: SLOT23
8428#[inline(always)]
8429#[cfg_attr(test, assert_instr(cmpyrwh))]
8430#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8431pub unsafe fn Q6_R_cmpyrwh_PR_s1_rnd_sat(rss: i64, rt: i32) -> i32 {
8432    hexagon_M4_cmpyr_wh(rss, rt)
8433}
8434
8435/// `Rd32=cmpyrwh(Rss32,Rt32*):<<1:rnd:sat`
8436///
8437/// Instruction Type: S_3op
8438/// Execution Slots: SLOT23
8439#[inline(always)]
8440#[cfg_attr(test, assert_instr(cmpyrwh))]
8441#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8442pub unsafe fn Q6_R_cmpyrwh_PR_conj_s1_rnd_sat(rss: i64, rt: i32) -> i32 {
8443    hexagon_M4_cmpyr_whc(rss, rt)
8444}
8445
8446/// `Rx32+=mpy(Rs32,Rt32):<<1:sat`
8447///
8448/// Instruction Type: M
8449/// Execution Slots: SLOT23
8450#[inline(always)]
8451#[cfg_attr(test, assert_instr(mpy))]
8452#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8453pub unsafe fn Q6_R_mpyacc_RR_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
8454    hexagon_M4_mac_up_s1_sat(rx, rs, rt)
8455}
8456
8457/// `Rd32=add(#u6,mpyi(Rs32,#U6))`
8458///
8459/// Instruction Type: ALU64
8460/// Execution Slots: SLOT23
8461#[inline(always)]
8462#[rustc_legacy_const_generics(0, 2)]
8463#[cfg_attr(test, assert_instr(add, IU6 = 0, IU6_2 = 0))]
8464#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8465pub unsafe fn Q6_R_add_mpyi_IRI<const IU6: u32, const IU6_2: u32>(rs: i32) -> i32 {
8466    static_assert_uimm_bits!(IU6, 6);
8467    static_assert_uimm_bits!(IU6_2, 6);
8468    hexagon_M4_mpyri_addi(IU6 as i32, rs, IU6_2 as i32)
8469}
8470
8471/// `Rd32=add(Ru32,mpyi(Rs32,#u6))`
8472///
8473/// Instruction Type: ALU64
8474/// Execution Slots: SLOT23
8475#[inline(always)]
8476#[rustc_legacy_const_generics(2)]
8477#[cfg_attr(test, assert_instr(add, IU6 = 0))]
8478#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8479pub unsafe fn Q6_R_add_mpyi_RRI<const IU6: u32>(ru: i32, rs: i32) -> i32 {
8480    static_assert_uimm_bits!(IU6, 6);
8481    hexagon_M4_mpyri_addr(ru, rs, IU6 as i32)
8482}
8483
8484/// `Rd32=add(Ru32,mpyi(#u6:2,Rs32))`
8485///
8486/// Instruction Type: ALU64
8487/// Execution Slots: SLOT23
8488#[inline(always)]
8489#[rustc_legacy_const_generics(1)]
8490#[cfg_attr(test, assert_instr(add, IU6_2 = 0))]
8491#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8492pub unsafe fn Q6_R_add_mpyi_RIR<const IU6_2: u32>(ru: i32, rs: i32) -> i32 {
8493    static_assert_uimm_bits!(IU6_2, 6);
8494    hexagon_M4_mpyri_addr_u2(ru, IU6_2 as i32, rs)
8495}
8496
8497/// `Rd32=add(#u6,mpyi(Rs32,Rt32))`
8498///
8499/// Instruction Type: ALU64
8500/// Execution Slots: SLOT23
8501#[inline(always)]
8502#[rustc_legacy_const_generics(0)]
8503#[cfg_attr(test, assert_instr(add, IU6 = 0))]
8504#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8505pub unsafe fn Q6_R_add_mpyi_IRR<const IU6: u32>(rs: i32, rt: i32) -> i32 {
8506    static_assert_uimm_bits!(IU6, 6);
8507    hexagon_M4_mpyrr_addi(IU6 as i32, rs, rt)
8508}
8509
8510/// `Ry32=add(Ru32,mpyi(Ry32,Rs32))`
8511///
8512/// Instruction Type: M
8513/// Execution Slots: SLOT23
8514#[inline(always)]
8515#[cfg_attr(test, assert_instr(add))]
8516#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8517pub unsafe fn Q6_R_add_mpyi_RRR(ru: i32, ry: i32, rs: i32) -> i32 {
8518    hexagon_M4_mpyrr_addr(ru, ry, rs)
8519}
8520
8521/// `Rx32-=mpy(Rs32,Rt32):<<1:sat`
8522///
8523/// Instruction Type: M
8524/// Execution Slots: SLOT23
8525#[inline(always)]
8526#[cfg_attr(test, assert_instr(mpy))]
8527#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8528pub unsafe fn Q6_R_mpynac_RR_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 {
8529    hexagon_M4_nac_up_s1_sat(rx, rs, rt)
8530}
8531
8532/// `Rx32|=and(Rs32,Rt32)`
8533///
8534/// Instruction Type: M
8535/// Execution Slots: SLOT23
8536#[inline(always)]
8537#[cfg_attr(test, assert_instr(and))]
8538#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8539pub unsafe fn Q6_R_andor_RR(rx: i32, rs: i32, rt: i32) -> i32 {
8540    hexagon_M4_or_and(rx, rs, rt)
8541}
8542
8543/// `Rx32|=and(Rs32,~Rt32)`
8544///
8545/// Instruction Type: M
8546/// Execution Slots: SLOT23
8547#[inline(always)]
8548#[cfg_attr(test, assert_instr(and))]
8549#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8550pub unsafe fn Q6_R_andor_RnR(rx: i32, rs: i32, rt: i32) -> i32 {
8551    hexagon_M4_or_andn(rx, rs, rt)
8552}
8553
8554/// `Rx32|=or(Rs32,Rt32)`
8555///
8556/// Instruction Type: M
8557/// Execution Slots: SLOT23
8558#[inline(always)]
8559#[cfg_attr(test, assert_instr(or))]
8560#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8561pub unsafe fn Q6_R_oror_RR(rx: i32, rs: i32, rt: i32) -> i32 {
8562    hexagon_M4_or_or(rx, rs, rt)
8563}
8564
8565/// `Rx32|=xor(Rs32,Rt32)`
8566///
8567/// Instruction Type: M
8568/// Execution Slots: SLOT23
8569#[inline(always)]
8570#[cfg_attr(test, assert_instr(xor))]
8571#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8572pub unsafe fn Q6_R_xoror_RR(rx: i32, rs: i32, rt: i32) -> i32 {
8573    hexagon_M4_or_xor(rx, rs, rt)
8574}
8575
8576/// `Rdd32=pmpyw(Rs32,Rt32)`
8577///
8578/// Instruction Type: M
8579/// Execution Slots: SLOT23
8580#[inline(always)]
8581#[cfg_attr(test, assert_instr(pmpyw))]
8582#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8583pub unsafe fn Q6_P_pmpyw_RR(rs: i32, rt: i32) -> i64 {
8584    hexagon_M4_pmpyw(rs, rt)
8585}
8586
8587/// `Rxx32^=pmpyw(Rs32,Rt32)`
8588///
8589/// Instruction Type: M
8590/// Execution Slots: SLOT23
8591#[inline(always)]
8592#[cfg_attr(test, assert_instr(pmpyw))]
8593#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8594pub unsafe fn Q6_P_pmpywxacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
8595    hexagon_M4_pmpyw_acc(rxx, rs, rt)
8596}
8597
8598/// `Rdd32=vpmpyh(Rs32,Rt32)`
8599///
8600/// Instruction Type: M
8601/// Execution Slots: SLOT23
8602#[inline(always)]
8603#[cfg_attr(test, assert_instr(vpmpyh))]
8604#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8605pub unsafe fn Q6_P_vpmpyh_RR(rs: i32, rt: i32) -> i64 {
8606    hexagon_M4_vpmpyh(rs, rt)
8607}
8608
8609/// `Rxx32^=vpmpyh(Rs32,Rt32)`
8610///
8611/// Instruction Type: M
8612/// Execution Slots: SLOT23
8613#[inline(always)]
8614#[cfg_attr(test, assert_instr(vpmpyh))]
8615#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8616pub unsafe fn Q6_P_vpmpyhxacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
8617    hexagon_M4_vpmpyh_acc(rxx, rs, rt)
8618}
8619
8620/// `Rxx32+=vrmpyweh(Rss32,Rtt32)`
8621///
8622/// Instruction Type: M
8623/// Execution Slots: SLOT23
8624#[inline(always)]
8625#[cfg_attr(test, assert_instr(vrmpyweh))]
8626#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8627pub unsafe fn Q6_P_vrmpywehacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
8628    hexagon_M4_vrmpyeh_acc_s0(rxx, rss, rtt)
8629}
8630
8631/// `Rxx32+=vrmpyweh(Rss32,Rtt32):<<1`
8632///
8633/// Instruction Type: M
8634/// Execution Slots: SLOT23
8635#[inline(always)]
8636#[cfg_attr(test, assert_instr(vrmpyweh))]
8637#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8638pub unsafe fn Q6_P_vrmpywehacc_PP_s1(rxx: i64, rss: i64, rtt: i64) -> i64 {
8639    hexagon_M4_vrmpyeh_acc_s1(rxx, rss, rtt)
8640}
8641
8642/// `Rdd32=vrmpyweh(Rss32,Rtt32)`
8643///
8644/// Instruction Type: M
8645/// Execution Slots: SLOT23
8646#[inline(always)]
8647#[cfg_attr(test, assert_instr(vrmpyweh))]
8648#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8649pub unsafe fn Q6_P_vrmpyweh_PP(rss: i64, rtt: i64) -> i64 {
8650    hexagon_M4_vrmpyeh_s0(rss, rtt)
8651}
8652
8653/// `Rdd32=vrmpyweh(Rss32,Rtt32):<<1`
8654///
8655/// Instruction Type: M
8656/// Execution Slots: SLOT23
8657#[inline(always)]
8658#[cfg_attr(test, assert_instr(vrmpyweh))]
8659#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8660pub unsafe fn Q6_P_vrmpyweh_PP_s1(rss: i64, rtt: i64) -> i64 {
8661    hexagon_M4_vrmpyeh_s1(rss, rtt)
8662}
8663
8664/// `Rxx32+=vrmpywoh(Rss32,Rtt32)`
8665///
8666/// Instruction Type: M
8667/// Execution Slots: SLOT23
8668#[inline(always)]
8669#[cfg_attr(test, assert_instr(vrmpywoh))]
8670#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8671pub unsafe fn Q6_P_vrmpywohacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
8672    hexagon_M4_vrmpyoh_acc_s0(rxx, rss, rtt)
8673}
8674
8675/// `Rxx32+=vrmpywoh(Rss32,Rtt32):<<1`
8676///
8677/// Instruction Type: M
8678/// Execution Slots: SLOT23
8679#[inline(always)]
8680#[cfg_attr(test, assert_instr(vrmpywoh))]
8681#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8682pub unsafe fn Q6_P_vrmpywohacc_PP_s1(rxx: i64, rss: i64, rtt: i64) -> i64 {
8683    hexagon_M4_vrmpyoh_acc_s1(rxx, rss, rtt)
8684}
8685
8686/// `Rdd32=vrmpywoh(Rss32,Rtt32)`
8687///
8688/// Instruction Type: M
8689/// Execution Slots: SLOT23
8690#[inline(always)]
8691#[cfg_attr(test, assert_instr(vrmpywoh))]
8692#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8693pub unsafe fn Q6_P_vrmpywoh_PP(rss: i64, rtt: i64) -> i64 {
8694    hexagon_M4_vrmpyoh_s0(rss, rtt)
8695}
8696
8697/// `Rdd32=vrmpywoh(Rss32,Rtt32):<<1`
8698///
8699/// Instruction Type: M
8700/// Execution Slots: SLOT23
8701#[inline(always)]
8702#[cfg_attr(test, assert_instr(vrmpywoh))]
8703#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8704pub unsafe fn Q6_P_vrmpywoh_PP_s1(rss: i64, rtt: i64) -> i64 {
8705    hexagon_M4_vrmpyoh_s1(rss, rtt)
8706}
8707
8708/// `Rx32^=and(Rs32,Rt32)`
8709///
8710/// Instruction Type: M
8711/// Execution Slots: SLOT23
8712#[inline(always)]
8713#[cfg_attr(test, assert_instr(and))]
8714#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8715pub unsafe fn Q6_R_andxacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
8716    hexagon_M4_xor_and(rx, rs, rt)
8717}
8718
8719/// `Rx32^=and(Rs32,~Rt32)`
8720///
8721/// Instruction Type: M
8722/// Execution Slots: SLOT23
8723#[inline(always)]
8724#[cfg_attr(test, assert_instr(and))]
8725#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8726pub unsafe fn Q6_R_andxacc_RnR(rx: i32, rs: i32, rt: i32) -> i32 {
8727    hexagon_M4_xor_andn(rx, rs, rt)
8728}
8729
8730/// `Rx32^=or(Rs32,Rt32)`
8731///
8732/// Instruction Type: M
8733/// Execution Slots: SLOT23
8734#[inline(always)]
8735#[cfg_attr(test, assert_instr(or))]
8736#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8737pub unsafe fn Q6_R_orxacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
8738    hexagon_M4_xor_or(rx, rs, rt)
8739}
8740
8741/// `Rxx32^=xor(Rss32,Rtt32)`
8742///
8743/// Instruction Type: S_3op
8744/// Execution Slots: SLOT23
8745#[inline(always)]
8746#[cfg_attr(test, assert_instr(xor))]
8747#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8748pub unsafe fn Q6_P_xorxacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
8749    hexagon_M4_xor_xacc(rxx, rss, rtt)
8750}
8751
8752/// `Rxx32+=vdmpybsu(Rss32,Rtt32):sat`
8753///
8754/// Instruction Type: M
8755/// Execution Slots: SLOT23
8756#[inline(always)]
8757#[cfg_attr(test, assert_instr(vdmpybsu))]
8758#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8759pub unsafe fn Q6_P_vdmpybsuacc_PP_sat(rxx: i64, rss: i64, rtt: i64) -> i64 {
8760    hexagon_M5_vdmacbsu(rxx, rss, rtt)
8761}
8762
8763/// `Rdd32=vdmpybsu(Rss32,Rtt32):sat`
8764///
8765/// Instruction Type: M
8766/// Execution Slots: SLOT23
8767#[inline(always)]
8768#[cfg_attr(test, assert_instr(vdmpybsu))]
8769#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8770pub unsafe fn Q6_P_vdmpybsu_PP_sat(rss: i64, rtt: i64) -> i64 {
8771    hexagon_M5_vdmpybsu(rss, rtt)
8772}
8773
8774/// `Rxx32+=vmpybsu(Rs32,Rt32)`
8775///
8776/// Instruction Type: M
8777/// Execution Slots: SLOT23
8778#[inline(always)]
8779#[cfg_attr(test, assert_instr(vmpybsu))]
8780#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8781pub unsafe fn Q6_P_vmpybsuacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
8782    hexagon_M5_vmacbsu(rxx, rs, rt)
8783}
8784
8785/// `Rxx32+=vmpybu(Rs32,Rt32)`
8786///
8787/// Instruction Type: M
8788/// Execution Slots: SLOT23
8789#[inline(always)]
8790#[cfg_attr(test, assert_instr(vmpybu))]
8791#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8792pub unsafe fn Q6_P_vmpybuacc_RR(rxx: i64, rs: i32, rt: i32) -> i64 {
8793    hexagon_M5_vmacbuu(rxx, rs, rt)
8794}
8795
8796/// `Rdd32=vmpybsu(Rs32,Rt32)`
8797///
8798/// Instruction Type: M
8799/// Execution Slots: SLOT23
8800#[inline(always)]
8801#[cfg_attr(test, assert_instr(vmpybsu))]
8802#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8803pub unsafe fn Q6_P_vmpybsu_RR(rs: i32, rt: i32) -> i64 {
8804    hexagon_M5_vmpybsu(rs, rt)
8805}
8806
8807/// `Rdd32=vmpybu(Rs32,Rt32)`
8808///
8809/// Instruction Type: M
8810/// Execution Slots: SLOT23
8811#[inline(always)]
8812#[cfg_attr(test, assert_instr(vmpybu))]
8813#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8814pub unsafe fn Q6_P_vmpybu_RR(rs: i32, rt: i32) -> i64 {
8815    hexagon_M5_vmpybuu(rs, rt)
8816}
8817
8818/// `Rxx32+=vrmpybsu(Rss32,Rtt32)`
8819///
8820/// Instruction Type: M
8821/// Execution Slots: SLOT23
8822#[inline(always)]
8823#[cfg_attr(test, assert_instr(vrmpybsu))]
8824#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8825pub unsafe fn Q6_P_vrmpybsuacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
8826    hexagon_M5_vrmacbsu(rxx, rss, rtt)
8827}
8828
8829/// `Rxx32+=vrmpybu(Rss32,Rtt32)`
8830///
8831/// Instruction Type: M
8832/// Execution Slots: SLOT23
8833#[inline(always)]
8834#[cfg_attr(test, assert_instr(vrmpybu))]
8835#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8836pub unsafe fn Q6_P_vrmpybuacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
8837    hexagon_M5_vrmacbuu(rxx, rss, rtt)
8838}
8839
8840/// `Rdd32=vrmpybsu(Rss32,Rtt32)`
8841///
8842/// Instruction Type: M
8843/// Execution Slots: SLOT23
8844#[inline(always)]
8845#[cfg_attr(test, assert_instr(vrmpybsu))]
8846#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8847pub unsafe fn Q6_P_vrmpybsu_PP(rss: i64, rtt: i64) -> i64 {
8848    hexagon_M5_vrmpybsu(rss, rtt)
8849}
8850
8851/// `Rdd32=vrmpybu(Rss32,Rtt32)`
8852///
8853/// Instruction Type: M
8854/// Execution Slots: SLOT23
8855#[inline(always)]
8856#[cfg_attr(test, assert_instr(vrmpybu))]
8857#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8858pub unsafe fn Q6_P_vrmpybu_PP(rss: i64, rtt: i64) -> i64 {
8859    hexagon_M5_vrmpybuu(rss, rtt)
8860}
8861
8862/// `Rd32=addasl(Rt32,Rs32,#u3)`
8863///
8864/// Instruction Type: S_3op
8865/// Execution Slots: SLOT23
8866#[inline(always)]
8867#[rustc_legacy_const_generics(2)]
8868#[cfg_attr(test, assert_instr(addasl, IU3 = 0))]
8869#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8870pub unsafe fn Q6_R_addasl_RRI<const IU3: u32>(rt: i32, rs: i32) -> i32 {
8871    static_assert_uimm_bits!(IU3, 3);
8872    hexagon_S2_addasl_rrri(rt, rs, IU3 as i32)
8873}
8874
8875/// `Rdd32=asl(Rss32,#u6)`
8876///
8877/// Instruction Type: S_2op
8878/// Execution Slots: SLOT23
8879#[inline(always)]
8880#[rustc_legacy_const_generics(1)]
8881#[cfg_attr(test, assert_instr(asl, IU6 = 0))]
8882#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8883pub unsafe fn Q6_P_asl_PI<const IU6: u32>(rss: i64) -> i64 {
8884    static_assert_uimm_bits!(IU6, 6);
8885    hexagon_S2_asl_i_p(rss, IU6 as i32)
8886}
8887
8888/// `Rxx32+=asl(Rss32,#u6)`
8889///
8890/// Instruction Type: S_2op
8891/// Execution Slots: SLOT23
8892#[inline(always)]
8893#[rustc_legacy_const_generics(2)]
8894#[cfg_attr(test, assert_instr(asl, IU6 = 0))]
8895#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8896pub unsafe fn Q6_P_aslacc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
8897    static_assert_uimm_bits!(IU6, 6);
8898    hexagon_S2_asl_i_p_acc(rxx, rss, IU6 as i32)
8899}
8900
8901/// `Rxx32&=asl(Rss32,#u6)`
8902///
8903/// Instruction Type: S_2op
8904/// Execution Slots: SLOT23
8905#[inline(always)]
8906#[rustc_legacy_const_generics(2)]
8907#[cfg_attr(test, assert_instr(asl, IU6 = 0))]
8908#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8909pub unsafe fn Q6_P_asland_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
8910    static_assert_uimm_bits!(IU6, 6);
8911    hexagon_S2_asl_i_p_and(rxx, rss, IU6 as i32)
8912}
8913
8914/// `Rxx32-=asl(Rss32,#u6)`
8915///
8916/// Instruction Type: S_2op
8917/// Execution Slots: SLOT23
8918#[inline(always)]
8919#[rustc_legacy_const_generics(2)]
8920#[cfg_attr(test, assert_instr(asl, IU6 = 0))]
8921#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8922pub unsafe fn Q6_P_aslnac_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
8923    static_assert_uimm_bits!(IU6, 6);
8924    hexagon_S2_asl_i_p_nac(rxx, rss, IU6 as i32)
8925}
8926
8927/// `Rxx32|=asl(Rss32,#u6)`
8928///
8929/// Instruction Type: S_2op
8930/// Execution Slots: SLOT23
8931#[inline(always)]
8932#[rustc_legacy_const_generics(2)]
8933#[cfg_attr(test, assert_instr(asl, IU6 = 0))]
8934#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8935pub unsafe fn Q6_P_aslor_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
8936    static_assert_uimm_bits!(IU6, 6);
8937    hexagon_S2_asl_i_p_or(rxx, rss, IU6 as i32)
8938}
8939
8940/// `Rxx32^=asl(Rss32,#u6)`
8941///
8942/// Instruction Type: S_2op
8943/// Execution Slots: SLOT23
8944#[inline(always)]
8945#[rustc_legacy_const_generics(2)]
8946#[cfg_attr(test, assert_instr(asl, IU6 = 0))]
8947#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8948pub unsafe fn Q6_P_aslxacc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
8949    static_assert_uimm_bits!(IU6, 6);
8950    hexagon_S2_asl_i_p_xacc(rxx, rss, IU6 as i32)
8951}
8952
8953/// `Rd32=asl(Rs32,#u5)`
8954///
8955/// Instruction Type: S_2op
8956/// Execution Slots: SLOT23
8957#[inline(always)]
8958#[rustc_legacy_const_generics(1)]
8959#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
8960#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8961pub unsafe fn Q6_R_asl_RI<const IU5: u32>(rs: i32) -> i32 {
8962    static_assert_uimm_bits!(IU5, 5);
8963    hexagon_S2_asl_i_r(rs, IU5 as i32)
8964}
8965
8966/// `Rx32+=asl(Rs32,#u5)`
8967///
8968/// Instruction Type: S_2op
8969/// Execution Slots: SLOT23
8970#[inline(always)]
8971#[rustc_legacy_const_generics(2)]
8972#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
8973#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8974pub unsafe fn Q6_R_aslacc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
8975    static_assert_uimm_bits!(IU5, 5);
8976    hexagon_S2_asl_i_r_acc(rx, rs, IU5 as i32)
8977}
8978
8979/// `Rx32&=asl(Rs32,#u5)`
8980///
8981/// Instruction Type: S_2op
8982/// Execution Slots: SLOT23
8983#[inline(always)]
8984#[rustc_legacy_const_generics(2)]
8985#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
8986#[unstable(feature = "stdarch_hexagon", issue = "151523")]
8987pub unsafe fn Q6_R_asland_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
8988    static_assert_uimm_bits!(IU5, 5);
8989    hexagon_S2_asl_i_r_and(rx, rs, IU5 as i32)
8990}
8991
8992/// `Rx32-=asl(Rs32,#u5)`
8993///
8994/// Instruction Type: S_2op
8995/// Execution Slots: SLOT23
8996#[inline(always)]
8997#[rustc_legacy_const_generics(2)]
8998#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
8999#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9000pub unsafe fn Q6_R_aslnac_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
9001    static_assert_uimm_bits!(IU5, 5);
9002    hexagon_S2_asl_i_r_nac(rx, rs, IU5 as i32)
9003}
9004
9005/// `Rx32|=asl(Rs32,#u5)`
9006///
9007/// Instruction Type: S_2op
9008/// Execution Slots: SLOT23
9009#[inline(always)]
9010#[rustc_legacy_const_generics(2)]
9011#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
9012#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9013pub unsafe fn Q6_R_aslor_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
9014    static_assert_uimm_bits!(IU5, 5);
9015    hexagon_S2_asl_i_r_or(rx, rs, IU5 as i32)
9016}
9017
9018/// `Rd32=asl(Rs32,#u5):sat`
9019///
9020/// Instruction Type: S_2op
9021/// Execution Slots: SLOT23
9022#[inline(always)]
9023#[rustc_legacy_const_generics(1)]
9024#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
9025#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9026pub unsafe fn Q6_R_asl_RI_sat<const IU5: u32>(rs: i32) -> i32 {
9027    static_assert_uimm_bits!(IU5, 5);
9028    hexagon_S2_asl_i_r_sat(rs, IU5 as i32)
9029}
9030
9031/// `Rx32^=asl(Rs32,#u5)`
9032///
9033/// Instruction Type: S_2op
9034/// Execution Slots: SLOT23
9035#[inline(always)]
9036#[rustc_legacy_const_generics(2)]
9037#[cfg_attr(test, assert_instr(asl, IU5 = 0))]
9038#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9039pub unsafe fn Q6_R_aslxacc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
9040    static_assert_uimm_bits!(IU5, 5);
9041    hexagon_S2_asl_i_r_xacc(rx, rs, IU5 as i32)
9042}
9043
9044/// `Rdd32=vaslh(Rss32,#u4)`
9045///
9046/// Instruction Type: S_2op
9047/// Execution Slots: SLOT23
9048#[inline(always)]
9049#[rustc_legacy_const_generics(1)]
9050#[cfg_attr(test, assert_instr(vaslh, IU4 = 0))]
9051#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9052pub unsafe fn Q6_P_vaslh_PI<const IU4: u32>(rss: i64) -> i64 {
9053    static_assert_uimm_bits!(IU4, 4);
9054    hexagon_S2_asl_i_vh(rss, IU4 as i32)
9055}
9056
9057/// `Rdd32=vaslw(Rss32,#u5)`
9058///
9059/// Instruction Type: S_2op
9060/// Execution Slots: SLOT23
9061#[inline(always)]
9062#[rustc_legacy_const_generics(1)]
9063#[cfg_attr(test, assert_instr(vaslw, IU5 = 0))]
9064#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9065pub unsafe fn Q6_P_vaslw_PI<const IU5: u32>(rss: i64) -> i64 {
9066    static_assert_uimm_bits!(IU5, 5);
9067    hexagon_S2_asl_i_vw(rss, IU5 as i32)
9068}
9069
9070/// `Rdd32=asl(Rss32,Rt32)`
9071///
9072/// Instruction Type: S_3op
9073/// Execution Slots: SLOT23
9074#[inline(always)]
9075#[cfg_attr(test, assert_instr(asl))]
9076#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9077pub unsafe fn Q6_P_asl_PR(rss: i64, rt: i32) -> i64 {
9078    hexagon_S2_asl_r_p(rss, rt)
9079}
9080
9081/// `Rxx32+=asl(Rss32,Rt32)`
9082///
9083/// Instruction Type: S_3op
9084/// Execution Slots: SLOT23
9085#[inline(always)]
9086#[cfg_attr(test, assert_instr(asl))]
9087#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9088pub unsafe fn Q6_P_aslacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9089    hexagon_S2_asl_r_p_acc(rxx, rss, rt)
9090}
9091
9092/// `Rxx32&=asl(Rss32,Rt32)`
9093///
9094/// Instruction Type: S_3op
9095/// Execution Slots: SLOT23
9096#[inline(always)]
9097#[cfg_attr(test, assert_instr(asl))]
9098#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9099pub unsafe fn Q6_P_asland_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9100    hexagon_S2_asl_r_p_and(rxx, rss, rt)
9101}
9102
9103/// `Rxx32-=asl(Rss32,Rt32)`
9104///
9105/// Instruction Type: S_3op
9106/// Execution Slots: SLOT23
9107#[inline(always)]
9108#[cfg_attr(test, assert_instr(asl))]
9109#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9110pub unsafe fn Q6_P_aslnac_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9111    hexagon_S2_asl_r_p_nac(rxx, rss, rt)
9112}
9113
9114/// `Rxx32|=asl(Rss32,Rt32)`
9115///
9116/// Instruction Type: S_3op
9117/// Execution Slots: SLOT23
9118#[inline(always)]
9119#[cfg_attr(test, assert_instr(asl))]
9120#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9121pub unsafe fn Q6_P_aslor_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9122    hexagon_S2_asl_r_p_or(rxx, rss, rt)
9123}
9124
9125/// `Rxx32^=asl(Rss32,Rt32)`
9126///
9127/// Instruction Type: S_3op
9128/// Execution Slots: SLOT23
9129#[inline(always)]
9130#[cfg_attr(test, assert_instr(asl))]
9131#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9132pub unsafe fn Q6_P_aslxacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9133    hexagon_S2_asl_r_p_xor(rxx, rss, rt)
9134}
9135
9136/// `Rd32=asl(Rs32,Rt32)`
9137///
9138/// Instruction Type: S_3op
9139/// Execution Slots: SLOT23
9140#[inline(always)]
9141#[cfg_attr(test, assert_instr(asl))]
9142#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9143pub unsafe fn Q6_R_asl_RR(rs: i32, rt: i32) -> i32 {
9144    hexagon_S2_asl_r_r(rs, rt)
9145}
9146
9147/// `Rx32+=asl(Rs32,Rt32)`
9148///
9149/// Instruction Type: S_3op
9150/// Execution Slots: SLOT23
9151#[inline(always)]
9152#[cfg_attr(test, assert_instr(asl))]
9153#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9154pub unsafe fn Q6_R_aslacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
9155    hexagon_S2_asl_r_r_acc(rx, rs, rt)
9156}
9157
9158/// `Rx32&=asl(Rs32,Rt32)`
9159///
9160/// Instruction Type: S_3op
9161/// Execution Slots: SLOT23
9162#[inline(always)]
9163#[cfg_attr(test, assert_instr(asl))]
9164#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9165pub unsafe fn Q6_R_asland_RR(rx: i32, rs: i32, rt: i32) -> i32 {
9166    hexagon_S2_asl_r_r_and(rx, rs, rt)
9167}
9168
9169/// `Rx32-=asl(Rs32,Rt32)`
9170///
9171/// Instruction Type: S_3op
9172/// Execution Slots: SLOT23
9173#[inline(always)]
9174#[cfg_attr(test, assert_instr(asl))]
9175#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9176pub unsafe fn Q6_R_aslnac_RR(rx: i32, rs: i32, rt: i32) -> i32 {
9177    hexagon_S2_asl_r_r_nac(rx, rs, rt)
9178}
9179
9180/// `Rx32|=asl(Rs32,Rt32)`
9181///
9182/// Instruction Type: S_3op
9183/// Execution Slots: SLOT23
9184#[inline(always)]
9185#[cfg_attr(test, assert_instr(asl))]
9186#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9187pub unsafe fn Q6_R_aslor_RR(rx: i32, rs: i32, rt: i32) -> i32 {
9188    hexagon_S2_asl_r_r_or(rx, rs, rt)
9189}
9190
9191/// `Rd32=asl(Rs32,Rt32):sat`
9192///
9193/// Instruction Type: S_3op
9194/// Execution Slots: SLOT23
9195#[inline(always)]
9196#[cfg_attr(test, assert_instr(asl))]
9197#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9198pub unsafe fn Q6_R_asl_RR_sat(rs: i32, rt: i32) -> i32 {
9199    hexagon_S2_asl_r_r_sat(rs, rt)
9200}
9201
9202/// `Rdd32=vaslh(Rss32,Rt32)`
9203///
9204/// Instruction Type: S_3op
9205/// Execution Slots: SLOT23
9206#[inline(always)]
9207#[cfg_attr(test, assert_instr(vaslh))]
9208#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9209pub unsafe fn Q6_P_vaslh_PR(rss: i64, rt: i32) -> i64 {
9210    hexagon_S2_asl_r_vh(rss, rt)
9211}
9212
9213/// `Rdd32=vaslw(Rss32,Rt32)`
9214///
9215/// Instruction Type: S_3op
9216/// Execution Slots: SLOT23
9217#[inline(always)]
9218#[cfg_attr(test, assert_instr(vaslw))]
9219#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9220pub unsafe fn Q6_P_vaslw_PR(rss: i64, rt: i32) -> i64 {
9221    hexagon_S2_asl_r_vw(rss, rt)
9222}
9223
9224/// `Rdd32=asr(Rss32,#u6)`
9225///
9226/// Instruction Type: S_2op
9227/// Execution Slots: SLOT23
9228#[inline(always)]
9229#[rustc_legacy_const_generics(1)]
9230#[cfg_attr(test, assert_instr(asr, IU6 = 0))]
9231#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9232pub unsafe fn Q6_P_asr_PI<const IU6: u32>(rss: i64) -> i64 {
9233    static_assert_uimm_bits!(IU6, 6);
9234    hexagon_S2_asr_i_p(rss, IU6 as i32)
9235}
9236
9237/// `Rxx32+=asr(Rss32,#u6)`
9238///
9239/// Instruction Type: S_2op
9240/// Execution Slots: SLOT23
9241#[inline(always)]
9242#[rustc_legacy_const_generics(2)]
9243#[cfg_attr(test, assert_instr(asr, IU6 = 0))]
9244#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9245pub unsafe fn Q6_P_asracc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
9246    static_assert_uimm_bits!(IU6, 6);
9247    hexagon_S2_asr_i_p_acc(rxx, rss, IU6 as i32)
9248}
9249
9250/// `Rxx32&=asr(Rss32,#u6)`
9251///
9252/// Instruction Type: S_2op
9253/// Execution Slots: SLOT23
9254#[inline(always)]
9255#[rustc_legacy_const_generics(2)]
9256#[cfg_attr(test, assert_instr(asr, IU6 = 0))]
9257#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9258pub unsafe fn Q6_P_asrand_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
9259    static_assert_uimm_bits!(IU6, 6);
9260    hexagon_S2_asr_i_p_and(rxx, rss, IU6 as i32)
9261}
9262
9263/// `Rxx32-=asr(Rss32,#u6)`
9264///
9265/// Instruction Type: S_2op
9266/// Execution Slots: SLOT23
9267#[inline(always)]
9268#[rustc_legacy_const_generics(2)]
9269#[cfg_attr(test, assert_instr(asr, IU6 = 0))]
9270#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9271pub unsafe fn Q6_P_asrnac_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
9272    static_assert_uimm_bits!(IU6, 6);
9273    hexagon_S2_asr_i_p_nac(rxx, rss, IU6 as i32)
9274}
9275
9276/// `Rxx32|=asr(Rss32,#u6)`
9277///
9278/// Instruction Type: S_2op
9279/// Execution Slots: SLOT23
9280#[inline(always)]
9281#[rustc_legacy_const_generics(2)]
9282#[cfg_attr(test, assert_instr(asr, IU6 = 0))]
9283#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9284pub unsafe fn Q6_P_asror_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
9285    static_assert_uimm_bits!(IU6, 6);
9286    hexagon_S2_asr_i_p_or(rxx, rss, IU6 as i32)
9287}
9288
9289/// `Rdd32=asr(Rss32,#u6):rnd`
9290///
9291/// Instruction Type: S_2op
9292/// Execution Slots: SLOT23
9293#[inline(always)]
9294#[rustc_legacy_const_generics(1)]
9295#[cfg_attr(test, assert_instr(asr, IU6 = 0))]
9296#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9297pub unsafe fn Q6_P_asr_PI_rnd<const IU6: u32>(rss: i64) -> i64 {
9298    static_assert_uimm_bits!(IU6, 6);
9299    hexagon_S2_asr_i_p_rnd(rss, IU6 as i32)
9300}
9301
9302/// `Rdd32=asrrnd(Rss32,#u6)`
9303///
9304/// Instruction Type: S_2op
9305/// Execution Slots: SLOT0123
9306#[inline(always)]
9307#[rustc_legacy_const_generics(1)]
9308#[cfg_attr(test, assert_instr(asrrnd, IU6 = 0))]
9309#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9310pub unsafe fn Q6_P_asrrnd_PI<const IU6: u32>(rss: i64) -> i64 {
9311    static_assert_uimm_bits!(IU6, 6);
9312    hexagon_S2_asr_i_p_rnd_goodsyntax(rss, IU6 as i32)
9313}
9314
9315/// `Rd32=asr(Rs32,#u5)`
9316///
9317/// Instruction Type: S_2op
9318/// Execution Slots: SLOT23
9319#[inline(always)]
9320#[rustc_legacy_const_generics(1)]
9321#[cfg_attr(test, assert_instr(asr, IU5 = 0))]
9322#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9323pub unsafe fn Q6_R_asr_RI<const IU5: u32>(rs: i32) -> i32 {
9324    static_assert_uimm_bits!(IU5, 5);
9325    hexagon_S2_asr_i_r(rs, IU5 as i32)
9326}
9327
9328/// `Rx32+=asr(Rs32,#u5)`
9329///
9330/// Instruction Type: S_2op
9331/// Execution Slots: SLOT23
9332#[inline(always)]
9333#[rustc_legacy_const_generics(2)]
9334#[cfg_attr(test, assert_instr(asr, IU5 = 0))]
9335#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9336pub unsafe fn Q6_R_asracc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
9337    static_assert_uimm_bits!(IU5, 5);
9338    hexagon_S2_asr_i_r_acc(rx, rs, IU5 as i32)
9339}
9340
9341/// `Rx32&=asr(Rs32,#u5)`
9342///
9343/// Instruction Type: S_2op
9344/// Execution Slots: SLOT23
9345#[inline(always)]
9346#[rustc_legacy_const_generics(2)]
9347#[cfg_attr(test, assert_instr(asr, IU5 = 0))]
9348#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9349pub unsafe fn Q6_R_asrand_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
9350    static_assert_uimm_bits!(IU5, 5);
9351    hexagon_S2_asr_i_r_and(rx, rs, IU5 as i32)
9352}
9353
9354/// `Rx32-=asr(Rs32,#u5)`
9355///
9356/// Instruction Type: S_2op
9357/// Execution Slots: SLOT23
9358#[inline(always)]
9359#[rustc_legacy_const_generics(2)]
9360#[cfg_attr(test, assert_instr(asr, IU5 = 0))]
9361#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9362pub unsafe fn Q6_R_asrnac_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
9363    static_assert_uimm_bits!(IU5, 5);
9364    hexagon_S2_asr_i_r_nac(rx, rs, IU5 as i32)
9365}
9366
9367/// `Rx32|=asr(Rs32,#u5)`
9368///
9369/// Instruction Type: S_2op
9370/// Execution Slots: SLOT23
9371#[inline(always)]
9372#[rustc_legacy_const_generics(2)]
9373#[cfg_attr(test, assert_instr(asr, IU5 = 0))]
9374#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9375pub unsafe fn Q6_R_asror_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
9376    static_assert_uimm_bits!(IU5, 5);
9377    hexagon_S2_asr_i_r_or(rx, rs, IU5 as i32)
9378}
9379
9380/// `Rd32=asr(Rs32,#u5):rnd`
9381///
9382/// Instruction Type: S_2op
9383/// Execution Slots: SLOT23
9384#[inline(always)]
9385#[rustc_legacy_const_generics(1)]
9386#[cfg_attr(test, assert_instr(asr, IU5 = 0))]
9387#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9388pub unsafe fn Q6_R_asr_RI_rnd<const IU5: u32>(rs: i32) -> i32 {
9389    static_assert_uimm_bits!(IU5, 5);
9390    hexagon_S2_asr_i_r_rnd(rs, IU5 as i32)
9391}
9392
9393/// `Rd32=asrrnd(Rs32,#u5)`
9394///
9395/// Instruction Type: S_2op
9396/// Execution Slots: SLOT0123
9397#[inline(always)]
9398#[rustc_legacy_const_generics(1)]
9399#[cfg_attr(test, assert_instr(asrrnd, IU5 = 0))]
9400#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9401pub unsafe fn Q6_R_asrrnd_RI<const IU5: u32>(rs: i32) -> i32 {
9402    static_assert_uimm_bits!(IU5, 5);
9403    hexagon_S2_asr_i_r_rnd_goodsyntax(rs, IU5 as i32)
9404}
9405
9406/// `Rd32=vasrw(Rss32,#u5)`
9407///
9408/// Instruction Type: S_2op
9409/// Execution Slots: SLOT23
9410#[inline(always)]
9411#[rustc_legacy_const_generics(1)]
9412#[cfg_attr(test, assert_instr(vasrw, IU5 = 0))]
9413#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9414pub unsafe fn Q6_R_vasrw_PI<const IU5: u32>(rss: i64) -> i32 {
9415    static_assert_uimm_bits!(IU5, 5);
9416    hexagon_S2_asr_i_svw_trun(rss, IU5 as i32)
9417}
9418
9419/// `Rdd32=vasrh(Rss32,#u4)`
9420///
9421/// Instruction Type: S_2op
9422/// Execution Slots: SLOT23
9423#[inline(always)]
9424#[rustc_legacy_const_generics(1)]
9425#[cfg_attr(test, assert_instr(vasrh, IU4 = 0))]
9426#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9427pub unsafe fn Q6_P_vasrh_PI<const IU4: u32>(rss: i64) -> i64 {
9428    static_assert_uimm_bits!(IU4, 4);
9429    hexagon_S2_asr_i_vh(rss, IU4 as i32)
9430}
9431
9432/// `Rdd32=vasrw(Rss32,#u5)`
9433///
9434/// Instruction Type: S_2op
9435/// Execution Slots: SLOT23
9436#[inline(always)]
9437#[rustc_legacy_const_generics(1)]
9438#[cfg_attr(test, assert_instr(vasrw, IU5 = 0))]
9439#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9440pub unsafe fn Q6_P_vasrw_PI<const IU5: u32>(rss: i64) -> i64 {
9441    static_assert_uimm_bits!(IU5, 5);
9442    hexagon_S2_asr_i_vw(rss, IU5 as i32)
9443}
9444
9445/// `Rdd32=asr(Rss32,Rt32)`
9446///
9447/// Instruction Type: S_3op
9448/// Execution Slots: SLOT23
9449#[inline(always)]
9450#[cfg_attr(test, assert_instr(asr))]
9451#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9452pub unsafe fn Q6_P_asr_PR(rss: i64, rt: i32) -> i64 {
9453    hexagon_S2_asr_r_p(rss, rt)
9454}
9455
9456/// `Rxx32+=asr(Rss32,Rt32)`
9457///
9458/// Instruction Type: S_3op
9459/// Execution Slots: SLOT23
9460#[inline(always)]
9461#[cfg_attr(test, assert_instr(asr))]
9462#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9463pub unsafe fn Q6_P_asracc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9464    hexagon_S2_asr_r_p_acc(rxx, rss, rt)
9465}
9466
9467/// `Rxx32&=asr(Rss32,Rt32)`
9468///
9469/// Instruction Type: S_3op
9470/// Execution Slots: SLOT23
9471#[inline(always)]
9472#[cfg_attr(test, assert_instr(asr))]
9473#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9474pub unsafe fn Q6_P_asrand_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9475    hexagon_S2_asr_r_p_and(rxx, rss, rt)
9476}
9477
9478/// `Rxx32-=asr(Rss32,Rt32)`
9479///
9480/// Instruction Type: S_3op
9481/// Execution Slots: SLOT23
9482#[inline(always)]
9483#[cfg_attr(test, assert_instr(asr))]
9484#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9485pub unsafe fn Q6_P_asrnac_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9486    hexagon_S2_asr_r_p_nac(rxx, rss, rt)
9487}
9488
9489/// `Rxx32|=asr(Rss32,Rt32)`
9490///
9491/// Instruction Type: S_3op
9492/// Execution Slots: SLOT23
9493#[inline(always)]
9494#[cfg_attr(test, assert_instr(asr))]
9495#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9496pub unsafe fn Q6_P_asror_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9497    hexagon_S2_asr_r_p_or(rxx, rss, rt)
9498}
9499
9500/// `Rxx32^=asr(Rss32,Rt32)`
9501///
9502/// Instruction Type: S_3op
9503/// Execution Slots: SLOT23
9504#[inline(always)]
9505#[cfg_attr(test, assert_instr(asr))]
9506#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9507pub unsafe fn Q6_P_asrxacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9508    hexagon_S2_asr_r_p_xor(rxx, rss, rt)
9509}
9510
9511/// `Rd32=asr(Rs32,Rt32)`
9512///
9513/// Instruction Type: S_3op
9514/// Execution Slots: SLOT23
9515#[inline(always)]
9516#[cfg_attr(test, assert_instr(asr))]
9517#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9518pub unsafe fn Q6_R_asr_RR(rs: i32, rt: i32) -> i32 {
9519    hexagon_S2_asr_r_r(rs, rt)
9520}
9521
9522/// `Rx32+=asr(Rs32,Rt32)`
9523///
9524/// Instruction Type: S_3op
9525/// Execution Slots: SLOT23
9526#[inline(always)]
9527#[cfg_attr(test, assert_instr(asr))]
9528#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9529pub unsafe fn Q6_R_asracc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
9530    hexagon_S2_asr_r_r_acc(rx, rs, rt)
9531}
9532
9533/// `Rx32&=asr(Rs32,Rt32)`
9534///
9535/// Instruction Type: S_3op
9536/// Execution Slots: SLOT23
9537#[inline(always)]
9538#[cfg_attr(test, assert_instr(asr))]
9539#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9540pub unsafe fn Q6_R_asrand_RR(rx: i32, rs: i32, rt: i32) -> i32 {
9541    hexagon_S2_asr_r_r_and(rx, rs, rt)
9542}
9543
9544/// `Rx32-=asr(Rs32,Rt32)`
9545///
9546/// Instruction Type: S_3op
9547/// Execution Slots: SLOT23
9548#[inline(always)]
9549#[cfg_attr(test, assert_instr(asr))]
9550#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9551pub unsafe fn Q6_R_asrnac_RR(rx: i32, rs: i32, rt: i32) -> i32 {
9552    hexagon_S2_asr_r_r_nac(rx, rs, rt)
9553}
9554
9555/// `Rx32|=asr(Rs32,Rt32)`
9556///
9557/// Instruction Type: S_3op
9558/// Execution Slots: SLOT23
9559#[inline(always)]
9560#[cfg_attr(test, assert_instr(asr))]
9561#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9562pub unsafe fn Q6_R_asror_RR(rx: i32, rs: i32, rt: i32) -> i32 {
9563    hexagon_S2_asr_r_r_or(rx, rs, rt)
9564}
9565
9566/// `Rd32=asr(Rs32,Rt32):sat`
9567///
9568/// Instruction Type: S_3op
9569/// Execution Slots: SLOT23
9570#[inline(always)]
9571#[cfg_attr(test, assert_instr(asr))]
9572#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9573pub unsafe fn Q6_R_asr_RR_sat(rs: i32, rt: i32) -> i32 {
9574    hexagon_S2_asr_r_r_sat(rs, rt)
9575}
9576
9577/// `Rd32=vasrw(Rss32,Rt32)`
9578///
9579/// Instruction Type: S_3op
9580/// Execution Slots: SLOT23
9581#[inline(always)]
9582#[cfg_attr(test, assert_instr(vasrw))]
9583#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9584pub unsafe fn Q6_R_vasrw_PR(rss: i64, rt: i32) -> i32 {
9585    hexagon_S2_asr_r_svw_trun(rss, rt)
9586}
9587
9588/// `Rdd32=vasrh(Rss32,Rt32)`
9589///
9590/// Instruction Type: S_3op
9591/// Execution Slots: SLOT23
9592#[inline(always)]
9593#[cfg_attr(test, assert_instr(vasrh))]
9594#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9595pub unsafe fn Q6_P_vasrh_PR(rss: i64, rt: i32) -> i64 {
9596    hexagon_S2_asr_r_vh(rss, rt)
9597}
9598
9599/// `Rdd32=vasrw(Rss32,Rt32)`
9600///
9601/// Instruction Type: S_3op
9602/// Execution Slots: SLOT23
9603#[inline(always)]
9604#[cfg_attr(test, assert_instr(vasrw))]
9605#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9606pub unsafe fn Q6_P_vasrw_PR(rss: i64, rt: i32) -> i64 {
9607    hexagon_S2_asr_r_vw(rss, rt)
9608}
9609
9610/// `Rd32=brev(Rs32)`
9611///
9612/// Instruction Type: S_2op
9613/// Execution Slots: SLOT23
9614#[inline(always)]
9615#[cfg_attr(test, assert_instr(brev))]
9616#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9617pub unsafe fn Q6_R_brev_R(rs: i32) -> i32 {
9618    hexagon_S2_brev(rs)
9619}
9620
9621/// `Rdd32=brev(Rss32)`
9622///
9623/// Instruction Type: S_2op
9624/// Execution Slots: SLOT23
9625#[inline(always)]
9626#[cfg_attr(test, assert_instr(brev))]
9627#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9628pub unsafe fn Q6_P_brev_P(rss: i64) -> i64 {
9629    hexagon_S2_brevp(rss)
9630}
9631
9632/// `Rd32=cl0(Rs32)`
9633///
9634/// Instruction Type: S_2op
9635/// Execution Slots: SLOT23
9636#[inline(always)]
9637#[cfg_attr(test, assert_instr(cl0))]
9638#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9639pub unsafe fn Q6_R_cl0_R(rs: i32) -> i32 {
9640    hexagon_S2_cl0(rs)
9641}
9642
9643/// `Rd32=cl0(Rss32)`
9644///
9645/// Instruction Type: S_2op
9646/// Execution Slots: SLOT23
9647#[inline(always)]
9648#[cfg_attr(test, assert_instr(cl0))]
9649#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9650pub unsafe fn Q6_R_cl0_P(rss: i64) -> i32 {
9651    hexagon_S2_cl0p(rss)
9652}
9653
9654/// `Rd32=cl1(Rs32)`
9655///
9656/// Instruction Type: S_2op
9657/// Execution Slots: SLOT23
9658#[inline(always)]
9659#[cfg_attr(test, assert_instr(cl1))]
9660#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9661pub unsafe fn Q6_R_cl1_R(rs: i32) -> i32 {
9662    hexagon_S2_cl1(rs)
9663}
9664
9665/// `Rd32=cl1(Rss32)`
9666///
9667/// Instruction Type: S_2op
9668/// Execution Slots: SLOT23
9669#[inline(always)]
9670#[cfg_attr(test, assert_instr(cl1))]
9671#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9672pub unsafe fn Q6_R_cl1_P(rss: i64) -> i32 {
9673    hexagon_S2_cl1p(rss)
9674}
9675
9676/// `Rd32=clb(Rs32)`
9677///
9678/// Instruction Type: S_2op
9679/// Execution Slots: SLOT23
9680#[inline(always)]
9681#[cfg_attr(test, assert_instr(clb))]
9682#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9683pub unsafe fn Q6_R_clb_R(rs: i32) -> i32 {
9684    hexagon_S2_clb(rs)
9685}
9686
9687/// `Rd32=normamt(Rs32)`
9688///
9689/// Instruction Type: S_2op
9690/// Execution Slots: SLOT23
9691#[inline(always)]
9692#[cfg_attr(test, assert_instr(normamt))]
9693#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9694pub unsafe fn Q6_R_normamt_R(rs: i32) -> i32 {
9695    hexagon_S2_clbnorm(rs)
9696}
9697
9698/// `Rd32=clb(Rss32)`
9699///
9700/// Instruction Type: S_2op
9701/// Execution Slots: SLOT23
9702#[inline(always)]
9703#[cfg_attr(test, assert_instr(clb))]
9704#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9705pub unsafe fn Q6_R_clb_P(rss: i64) -> i32 {
9706    hexagon_S2_clbp(rss)
9707}
9708
9709/// `Rd32=clrbit(Rs32,#u5)`
9710///
9711/// Instruction Type: S_2op
9712/// Execution Slots: SLOT23
9713#[inline(always)]
9714#[rustc_legacy_const_generics(1)]
9715#[cfg_attr(test, assert_instr(clrbit, IU5 = 0))]
9716#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9717pub unsafe fn Q6_R_clrbit_RI<const IU5: u32>(rs: i32) -> i32 {
9718    static_assert_uimm_bits!(IU5, 5);
9719    hexagon_S2_clrbit_i(rs, IU5 as i32)
9720}
9721
9722/// `Rd32=clrbit(Rs32,Rt32)`
9723///
9724/// Instruction Type: S_3op
9725/// Execution Slots: SLOT23
9726#[inline(always)]
9727#[cfg_attr(test, assert_instr(clrbit))]
9728#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9729pub unsafe fn Q6_R_clrbit_RR(rs: i32, rt: i32) -> i32 {
9730    hexagon_S2_clrbit_r(rs, rt)
9731}
9732
9733/// `Rd32=ct0(Rs32)`
9734///
9735/// Instruction Type: S_2op
9736/// Execution Slots: SLOT23
9737#[inline(always)]
9738#[cfg_attr(test, assert_instr(ct0))]
9739#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9740pub unsafe fn Q6_R_ct0_R(rs: i32) -> i32 {
9741    hexagon_S2_ct0(rs)
9742}
9743
9744/// `Rd32=ct0(Rss32)`
9745///
9746/// Instruction Type: S_2op
9747/// Execution Slots: SLOT23
9748#[inline(always)]
9749#[cfg_attr(test, assert_instr(ct0))]
9750#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9751pub unsafe fn Q6_R_ct0_P(rss: i64) -> i32 {
9752    hexagon_S2_ct0p(rss)
9753}
9754
9755/// `Rd32=ct1(Rs32)`
9756///
9757/// Instruction Type: S_2op
9758/// Execution Slots: SLOT23
9759#[inline(always)]
9760#[cfg_attr(test, assert_instr(ct1))]
9761#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9762pub unsafe fn Q6_R_ct1_R(rs: i32) -> i32 {
9763    hexagon_S2_ct1(rs)
9764}
9765
9766/// `Rd32=ct1(Rss32)`
9767///
9768/// Instruction Type: S_2op
9769/// Execution Slots: SLOT23
9770#[inline(always)]
9771#[cfg_attr(test, assert_instr(ct1))]
9772#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9773pub unsafe fn Q6_R_ct1_P(rss: i64) -> i32 {
9774    hexagon_S2_ct1p(rss)
9775}
9776
9777/// `Rdd32=deinterleave(Rss32)`
9778///
9779/// Instruction Type: S_2op
9780/// Execution Slots: SLOT23
9781#[inline(always)]
9782#[cfg_attr(test, assert_instr(deinterleave))]
9783#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9784pub unsafe fn Q6_P_deinterleave_P(rss: i64) -> i64 {
9785    hexagon_S2_deinterleave(rss)
9786}
9787
9788/// `Rd32=extractu(Rs32,#u5,#U5)`
9789///
9790/// Instruction Type: S_2op
9791/// Execution Slots: SLOT23
9792#[inline(always)]
9793#[rustc_legacy_const_generics(1, 2)]
9794#[cfg_attr(test, assert_instr(extractu, IU5 = 0, IU5_2 = 0))]
9795#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9796pub unsafe fn Q6_R_extractu_RII<const IU5: u32, const IU5_2: u32>(rs: i32) -> i32 {
9797    static_assert_uimm_bits!(IU5, 5);
9798    static_assert_uimm_bits!(IU5_2, 5);
9799    hexagon_S2_extractu(rs, IU5 as i32, IU5_2 as i32)
9800}
9801
9802/// `Rd32=extractu(Rs32,Rtt32)`
9803///
9804/// Instruction Type: S_3op
9805/// Execution Slots: SLOT23
9806#[inline(always)]
9807#[cfg_attr(test, assert_instr(extractu))]
9808#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9809pub unsafe fn Q6_R_extractu_RP(rs: i32, rtt: i64) -> i32 {
9810    hexagon_S2_extractu_rp(rs, rtt)
9811}
9812
9813/// `Rdd32=extractu(Rss32,#u6,#U6)`
9814///
9815/// Instruction Type: S_2op
9816/// Execution Slots: SLOT23
9817#[inline(always)]
9818#[rustc_legacy_const_generics(1, 2)]
9819#[cfg_attr(test, assert_instr(extractu, IU6 = 0, IU6_2 = 0))]
9820#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9821pub unsafe fn Q6_P_extractu_PII<const IU6: u32, const IU6_2: u32>(rss: i64) -> i64 {
9822    static_assert_uimm_bits!(IU6, 6);
9823    static_assert_uimm_bits!(IU6_2, 6);
9824    hexagon_S2_extractup(rss, IU6 as i32, IU6_2 as i32)
9825}
9826
9827/// `Rdd32=extractu(Rss32,Rtt32)`
9828///
9829/// Instruction Type: S_3op
9830/// Execution Slots: SLOT23
9831#[inline(always)]
9832#[cfg_attr(test, assert_instr(extractu))]
9833#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9834pub unsafe fn Q6_P_extractu_PP(rss: i64, rtt: i64) -> i64 {
9835    hexagon_S2_extractup_rp(rss, rtt)
9836}
9837
9838/// `Rx32=insert(Rs32,#u5,#U5)`
9839///
9840/// Instruction Type: S_2op
9841/// Execution Slots: SLOT23
9842#[inline(always)]
9843#[rustc_legacy_const_generics(2, 3)]
9844#[cfg_attr(test, assert_instr(insert, IU5 = 0, IU5_2 = 0))]
9845#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9846pub unsafe fn Q6_R_insert_RII<const IU5: u32, const IU5_2: u32>(rx: i32, rs: i32) -> i32 {
9847    static_assert_uimm_bits!(IU5, 5);
9848    static_assert_uimm_bits!(IU5_2, 5);
9849    hexagon_S2_insert(rx, rs, IU5 as i32, IU5_2 as i32)
9850}
9851
9852/// `Rx32=insert(Rs32,Rtt32)`
9853///
9854/// Instruction Type: S_3op
9855/// Execution Slots: SLOT23
9856#[inline(always)]
9857#[cfg_attr(test, assert_instr(insert))]
9858#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9859pub unsafe fn Q6_R_insert_RP(rx: i32, rs: i32, rtt: i64) -> i32 {
9860    hexagon_S2_insert_rp(rx, rs, rtt)
9861}
9862
9863/// `Rxx32=insert(Rss32,#u6,#U6)`
9864///
9865/// Instruction Type: S_2op
9866/// Execution Slots: SLOT23
9867#[inline(always)]
9868#[rustc_legacy_const_generics(2, 3)]
9869#[cfg_attr(test, assert_instr(insert, IU6 = 0, IU6_2 = 0))]
9870#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9871pub unsafe fn Q6_P_insert_PII<const IU6: u32, const IU6_2: u32>(rxx: i64, rss: i64) -> i64 {
9872    static_assert_uimm_bits!(IU6, 6);
9873    static_assert_uimm_bits!(IU6_2, 6);
9874    hexagon_S2_insertp(rxx, rss, IU6 as i32, IU6_2 as i32)
9875}
9876
9877/// `Rxx32=insert(Rss32,Rtt32)`
9878///
9879/// Instruction Type: S_3op
9880/// Execution Slots: SLOT23
9881#[inline(always)]
9882#[cfg_attr(test, assert_instr(insert))]
9883#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9884pub unsafe fn Q6_P_insert_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
9885    hexagon_S2_insertp_rp(rxx, rss, rtt)
9886}
9887
9888/// `Rdd32=interleave(Rss32)`
9889///
9890/// Instruction Type: S_2op
9891/// Execution Slots: SLOT23
9892#[inline(always)]
9893#[cfg_attr(test, assert_instr(interleave))]
9894#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9895pub unsafe fn Q6_P_interleave_P(rss: i64) -> i64 {
9896    hexagon_S2_interleave(rss)
9897}
9898
9899/// `Rdd32=lfs(Rss32,Rtt32)`
9900///
9901/// Instruction Type: S_3op
9902/// Execution Slots: SLOT23
9903#[inline(always)]
9904#[cfg_attr(test, assert_instr(lfs))]
9905#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9906pub unsafe fn Q6_P_lfs_PP(rss: i64, rtt: i64) -> i64 {
9907    hexagon_S2_lfsp(rss, rtt)
9908}
9909
9910/// `Rdd32=lsl(Rss32,Rt32)`
9911///
9912/// Instruction Type: S_3op
9913/// Execution Slots: SLOT23
9914#[inline(always)]
9915#[cfg_attr(test, assert_instr(lsl))]
9916#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9917pub unsafe fn Q6_P_lsl_PR(rss: i64, rt: i32) -> i64 {
9918    hexagon_S2_lsl_r_p(rss, rt)
9919}
9920
9921/// `Rxx32+=lsl(Rss32,Rt32)`
9922///
9923/// Instruction Type: S_3op
9924/// Execution Slots: SLOT23
9925#[inline(always)]
9926#[cfg_attr(test, assert_instr(lsl))]
9927#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9928pub unsafe fn Q6_P_lslacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9929    hexagon_S2_lsl_r_p_acc(rxx, rss, rt)
9930}
9931
9932/// `Rxx32&=lsl(Rss32,Rt32)`
9933///
9934/// Instruction Type: S_3op
9935/// Execution Slots: SLOT23
9936#[inline(always)]
9937#[cfg_attr(test, assert_instr(lsl))]
9938#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9939pub unsafe fn Q6_P_lsland_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9940    hexagon_S2_lsl_r_p_and(rxx, rss, rt)
9941}
9942
9943/// `Rxx32-=lsl(Rss32,Rt32)`
9944///
9945/// Instruction Type: S_3op
9946/// Execution Slots: SLOT23
9947#[inline(always)]
9948#[cfg_attr(test, assert_instr(lsl))]
9949#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9950pub unsafe fn Q6_P_lslnac_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9951    hexagon_S2_lsl_r_p_nac(rxx, rss, rt)
9952}
9953
9954/// `Rxx32|=lsl(Rss32,Rt32)`
9955///
9956/// Instruction Type: S_3op
9957/// Execution Slots: SLOT23
9958#[inline(always)]
9959#[cfg_attr(test, assert_instr(lsl))]
9960#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9961pub unsafe fn Q6_P_lslor_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9962    hexagon_S2_lsl_r_p_or(rxx, rss, rt)
9963}
9964
9965/// `Rxx32^=lsl(Rss32,Rt32)`
9966///
9967/// Instruction Type: S_3op
9968/// Execution Slots: SLOT23
9969#[inline(always)]
9970#[cfg_attr(test, assert_instr(lsl))]
9971#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9972pub unsafe fn Q6_P_lslxacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
9973    hexagon_S2_lsl_r_p_xor(rxx, rss, rt)
9974}
9975
9976/// `Rd32=lsl(Rs32,Rt32)`
9977///
9978/// Instruction Type: S_3op
9979/// Execution Slots: SLOT23
9980#[inline(always)]
9981#[cfg_attr(test, assert_instr(lsl))]
9982#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9983pub unsafe fn Q6_R_lsl_RR(rs: i32, rt: i32) -> i32 {
9984    hexagon_S2_lsl_r_r(rs, rt)
9985}
9986
9987/// `Rx32+=lsl(Rs32,Rt32)`
9988///
9989/// Instruction Type: S_3op
9990/// Execution Slots: SLOT23
9991#[inline(always)]
9992#[cfg_attr(test, assert_instr(lsl))]
9993#[unstable(feature = "stdarch_hexagon", issue = "151523")]
9994pub unsafe fn Q6_R_lslacc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
9995    hexagon_S2_lsl_r_r_acc(rx, rs, rt)
9996}
9997
9998/// `Rx32&=lsl(Rs32,Rt32)`
9999///
10000/// Instruction Type: S_3op
10001/// Execution Slots: SLOT23
10002#[inline(always)]
10003#[cfg_attr(test, assert_instr(lsl))]
10004#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10005pub unsafe fn Q6_R_lsland_RR(rx: i32, rs: i32, rt: i32) -> i32 {
10006    hexagon_S2_lsl_r_r_and(rx, rs, rt)
10007}
10008
10009/// `Rx32-=lsl(Rs32,Rt32)`
10010///
10011/// Instruction Type: S_3op
10012/// Execution Slots: SLOT23
10013#[inline(always)]
10014#[cfg_attr(test, assert_instr(lsl))]
10015#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10016pub unsafe fn Q6_R_lslnac_RR(rx: i32, rs: i32, rt: i32) -> i32 {
10017    hexagon_S2_lsl_r_r_nac(rx, rs, rt)
10018}
10019
10020/// `Rx32|=lsl(Rs32,Rt32)`
10021///
10022/// Instruction Type: S_3op
10023/// Execution Slots: SLOT23
10024#[inline(always)]
10025#[cfg_attr(test, assert_instr(lsl))]
10026#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10027pub unsafe fn Q6_R_lslor_RR(rx: i32, rs: i32, rt: i32) -> i32 {
10028    hexagon_S2_lsl_r_r_or(rx, rs, rt)
10029}
10030
10031/// `Rdd32=vlslh(Rss32,Rt32)`
10032///
10033/// Instruction Type: S_3op
10034/// Execution Slots: SLOT23
10035#[inline(always)]
10036#[cfg_attr(test, assert_instr(vlslh))]
10037#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10038pub unsafe fn Q6_P_vlslh_PR(rss: i64, rt: i32) -> i64 {
10039    hexagon_S2_lsl_r_vh(rss, rt)
10040}
10041
10042/// `Rdd32=vlslw(Rss32,Rt32)`
10043///
10044/// Instruction Type: S_3op
10045/// Execution Slots: SLOT23
10046#[inline(always)]
10047#[cfg_attr(test, assert_instr(vlslw))]
10048#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10049pub unsafe fn Q6_P_vlslw_PR(rss: i64, rt: i32) -> i64 {
10050    hexagon_S2_lsl_r_vw(rss, rt)
10051}
10052
10053/// `Rdd32=lsr(Rss32,#u6)`
10054///
10055/// Instruction Type: S_2op
10056/// Execution Slots: SLOT23
10057#[inline(always)]
10058#[rustc_legacy_const_generics(1)]
10059#[cfg_attr(test, assert_instr(lsr, IU6 = 0))]
10060#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10061pub unsafe fn Q6_P_lsr_PI<const IU6: u32>(rss: i64) -> i64 {
10062    static_assert_uimm_bits!(IU6, 6);
10063    hexagon_S2_lsr_i_p(rss, IU6 as i32)
10064}
10065
10066/// `Rxx32+=lsr(Rss32,#u6)`
10067///
10068/// Instruction Type: S_2op
10069/// Execution Slots: SLOT23
10070#[inline(always)]
10071#[rustc_legacy_const_generics(2)]
10072#[cfg_attr(test, assert_instr(lsr, IU6 = 0))]
10073#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10074pub unsafe fn Q6_P_lsracc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
10075    static_assert_uimm_bits!(IU6, 6);
10076    hexagon_S2_lsr_i_p_acc(rxx, rss, IU6 as i32)
10077}
10078
10079/// `Rxx32&=lsr(Rss32,#u6)`
10080///
10081/// Instruction Type: S_2op
10082/// Execution Slots: SLOT23
10083#[inline(always)]
10084#[rustc_legacy_const_generics(2)]
10085#[cfg_attr(test, assert_instr(lsr, IU6 = 0))]
10086#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10087pub unsafe fn Q6_P_lsrand_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
10088    static_assert_uimm_bits!(IU6, 6);
10089    hexagon_S2_lsr_i_p_and(rxx, rss, IU6 as i32)
10090}
10091
10092/// `Rxx32-=lsr(Rss32,#u6)`
10093///
10094/// Instruction Type: S_2op
10095/// Execution Slots: SLOT23
10096#[inline(always)]
10097#[rustc_legacy_const_generics(2)]
10098#[cfg_attr(test, assert_instr(lsr, IU6 = 0))]
10099#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10100pub unsafe fn Q6_P_lsrnac_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
10101    static_assert_uimm_bits!(IU6, 6);
10102    hexagon_S2_lsr_i_p_nac(rxx, rss, IU6 as i32)
10103}
10104
10105/// `Rxx32|=lsr(Rss32,#u6)`
10106///
10107/// Instruction Type: S_2op
10108/// Execution Slots: SLOT23
10109#[inline(always)]
10110#[rustc_legacy_const_generics(2)]
10111#[cfg_attr(test, assert_instr(lsr, IU6 = 0))]
10112#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10113pub unsafe fn Q6_P_lsror_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
10114    static_assert_uimm_bits!(IU6, 6);
10115    hexagon_S2_lsr_i_p_or(rxx, rss, IU6 as i32)
10116}
10117
10118/// `Rxx32^=lsr(Rss32,#u6)`
10119///
10120/// Instruction Type: S_2op
10121/// Execution Slots: SLOT23
10122#[inline(always)]
10123#[rustc_legacy_const_generics(2)]
10124#[cfg_attr(test, assert_instr(lsr, IU6 = 0))]
10125#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10126pub unsafe fn Q6_P_lsrxacc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
10127    static_assert_uimm_bits!(IU6, 6);
10128    hexagon_S2_lsr_i_p_xacc(rxx, rss, IU6 as i32)
10129}
10130
10131/// `Rd32=lsr(Rs32,#u5)`
10132///
10133/// Instruction Type: S_2op
10134/// Execution Slots: SLOT23
10135#[inline(always)]
10136#[rustc_legacy_const_generics(1)]
10137#[cfg_attr(test, assert_instr(lsr, IU5 = 0))]
10138#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10139pub unsafe fn Q6_R_lsr_RI<const IU5: u32>(rs: i32) -> i32 {
10140    static_assert_uimm_bits!(IU5, 5);
10141    hexagon_S2_lsr_i_r(rs, IU5 as i32)
10142}
10143
10144/// `Rx32+=lsr(Rs32,#u5)`
10145///
10146/// Instruction Type: S_2op
10147/// Execution Slots: SLOT23
10148#[inline(always)]
10149#[rustc_legacy_const_generics(2)]
10150#[cfg_attr(test, assert_instr(lsr, IU5 = 0))]
10151#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10152pub unsafe fn Q6_R_lsracc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
10153    static_assert_uimm_bits!(IU5, 5);
10154    hexagon_S2_lsr_i_r_acc(rx, rs, IU5 as i32)
10155}
10156
10157/// `Rx32&=lsr(Rs32,#u5)`
10158///
10159/// Instruction Type: S_2op
10160/// Execution Slots: SLOT23
10161#[inline(always)]
10162#[rustc_legacy_const_generics(2)]
10163#[cfg_attr(test, assert_instr(lsr, IU5 = 0))]
10164#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10165pub unsafe fn Q6_R_lsrand_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
10166    static_assert_uimm_bits!(IU5, 5);
10167    hexagon_S2_lsr_i_r_and(rx, rs, IU5 as i32)
10168}
10169
10170/// `Rx32-=lsr(Rs32,#u5)`
10171///
10172/// Instruction Type: S_2op
10173/// Execution Slots: SLOT23
10174#[inline(always)]
10175#[rustc_legacy_const_generics(2)]
10176#[cfg_attr(test, assert_instr(lsr, IU5 = 0))]
10177#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10178pub unsafe fn Q6_R_lsrnac_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
10179    static_assert_uimm_bits!(IU5, 5);
10180    hexagon_S2_lsr_i_r_nac(rx, rs, IU5 as i32)
10181}
10182
10183/// `Rx32|=lsr(Rs32,#u5)`
10184///
10185/// Instruction Type: S_2op
10186/// Execution Slots: SLOT23
10187#[inline(always)]
10188#[rustc_legacy_const_generics(2)]
10189#[cfg_attr(test, assert_instr(lsr, IU5 = 0))]
10190#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10191pub unsafe fn Q6_R_lsror_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
10192    static_assert_uimm_bits!(IU5, 5);
10193    hexagon_S2_lsr_i_r_or(rx, rs, IU5 as i32)
10194}
10195
10196/// `Rx32^=lsr(Rs32,#u5)`
10197///
10198/// Instruction Type: S_2op
10199/// Execution Slots: SLOT23
10200#[inline(always)]
10201#[rustc_legacy_const_generics(2)]
10202#[cfg_attr(test, assert_instr(lsr, IU5 = 0))]
10203#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10204pub unsafe fn Q6_R_lsrxacc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
10205    static_assert_uimm_bits!(IU5, 5);
10206    hexagon_S2_lsr_i_r_xacc(rx, rs, IU5 as i32)
10207}
10208
10209/// `Rdd32=vlsrh(Rss32,#u4)`
10210///
10211/// Instruction Type: S_2op
10212/// Execution Slots: SLOT23
10213#[inline(always)]
10214#[rustc_legacy_const_generics(1)]
10215#[cfg_attr(test, assert_instr(vlsrh, IU4 = 0))]
10216#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10217pub unsafe fn Q6_P_vlsrh_PI<const IU4: u32>(rss: i64) -> i64 {
10218    static_assert_uimm_bits!(IU4, 4);
10219    hexagon_S2_lsr_i_vh(rss, IU4 as i32)
10220}
10221
10222/// `Rdd32=vlsrw(Rss32,#u5)`
10223///
10224/// Instruction Type: S_2op
10225/// Execution Slots: SLOT23
10226#[inline(always)]
10227#[rustc_legacy_const_generics(1)]
10228#[cfg_attr(test, assert_instr(vlsrw, IU5 = 0))]
10229#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10230pub unsafe fn Q6_P_vlsrw_PI<const IU5: u32>(rss: i64) -> i64 {
10231    static_assert_uimm_bits!(IU5, 5);
10232    hexagon_S2_lsr_i_vw(rss, IU5 as i32)
10233}
10234
10235/// `Rdd32=lsr(Rss32,Rt32)`
10236///
10237/// Instruction Type: S_3op
10238/// Execution Slots: SLOT23
10239#[inline(always)]
10240#[cfg_attr(test, assert_instr(lsr))]
10241#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10242pub unsafe fn Q6_P_lsr_PR(rss: i64, rt: i32) -> i64 {
10243    hexagon_S2_lsr_r_p(rss, rt)
10244}
10245
10246/// `Rxx32+=lsr(Rss32,Rt32)`
10247///
10248/// Instruction Type: S_3op
10249/// Execution Slots: SLOT23
10250#[inline(always)]
10251#[cfg_attr(test, assert_instr(lsr))]
10252#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10253pub unsafe fn Q6_P_lsracc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
10254    hexagon_S2_lsr_r_p_acc(rxx, rss, rt)
10255}
10256
10257/// `Rxx32&=lsr(Rss32,Rt32)`
10258///
10259/// Instruction Type: S_3op
10260/// Execution Slots: SLOT23
10261#[inline(always)]
10262#[cfg_attr(test, assert_instr(lsr))]
10263#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10264pub unsafe fn Q6_P_lsrand_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
10265    hexagon_S2_lsr_r_p_and(rxx, rss, rt)
10266}
10267
10268/// `Rxx32-=lsr(Rss32,Rt32)`
10269///
10270/// Instruction Type: S_3op
10271/// Execution Slots: SLOT23
10272#[inline(always)]
10273#[cfg_attr(test, assert_instr(lsr))]
10274#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10275pub unsafe fn Q6_P_lsrnac_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
10276    hexagon_S2_lsr_r_p_nac(rxx, rss, rt)
10277}
10278
10279/// `Rxx32|=lsr(Rss32,Rt32)`
10280///
10281/// Instruction Type: S_3op
10282/// Execution Slots: SLOT23
10283#[inline(always)]
10284#[cfg_attr(test, assert_instr(lsr))]
10285#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10286pub unsafe fn Q6_P_lsror_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
10287    hexagon_S2_lsr_r_p_or(rxx, rss, rt)
10288}
10289
10290/// `Rxx32^=lsr(Rss32,Rt32)`
10291///
10292/// Instruction Type: S_3op
10293/// Execution Slots: SLOT23
10294#[inline(always)]
10295#[cfg_attr(test, assert_instr(lsr))]
10296#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10297pub unsafe fn Q6_P_lsrxacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
10298    hexagon_S2_lsr_r_p_xor(rxx, rss, rt)
10299}
10300
10301/// `Rd32=lsr(Rs32,Rt32)`
10302///
10303/// Instruction Type: S_3op
10304/// Execution Slots: SLOT23
10305#[inline(always)]
10306#[cfg_attr(test, assert_instr(lsr))]
10307#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10308pub unsafe fn Q6_R_lsr_RR(rs: i32, rt: i32) -> i32 {
10309    hexagon_S2_lsr_r_r(rs, rt)
10310}
10311
10312/// `Rx32+=lsr(Rs32,Rt32)`
10313///
10314/// Instruction Type: S_3op
10315/// Execution Slots: SLOT23
10316#[inline(always)]
10317#[cfg_attr(test, assert_instr(lsr))]
10318#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10319pub unsafe fn Q6_R_lsracc_RR(rx: i32, rs: i32, rt: i32) -> i32 {
10320    hexagon_S2_lsr_r_r_acc(rx, rs, rt)
10321}
10322
10323/// `Rx32&=lsr(Rs32,Rt32)`
10324///
10325/// Instruction Type: S_3op
10326/// Execution Slots: SLOT23
10327#[inline(always)]
10328#[cfg_attr(test, assert_instr(lsr))]
10329#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10330pub unsafe fn Q6_R_lsrand_RR(rx: i32, rs: i32, rt: i32) -> i32 {
10331    hexagon_S2_lsr_r_r_and(rx, rs, rt)
10332}
10333
10334/// `Rx32-=lsr(Rs32,Rt32)`
10335///
10336/// Instruction Type: S_3op
10337/// Execution Slots: SLOT23
10338#[inline(always)]
10339#[cfg_attr(test, assert_instr(lsr))]
10340#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10341pub unsafe fn Q6_R_lsrnac_RR(rx: i32, rs: i32, rt: i32) -> i32 {
10342    hexagon_S2_lsr_r_r_nac(rx, rs, rt)
10343}
10344
10345/// `Rx32|=lsr(Rs32,Rt32)`
10346///
10347/// Instruction Type: S_3op
10348/// Execution Slots: SLOT23
10349#[inline(always)]
10350#[cfg_attr(test, assert_instr(lsr))]
10351#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10352pub unsafe fn Q6_R_lsror_RR(rx: i32, rs: i32, rt: i32) -> i32 {
10353    hexagon_S2_lsr_r_r_or(rx, rs, rt)
10354}
10355
10356/// `Rdd32=vlsrh(Rss32,Rt32)`
10357///
10358/// Instruction Type: S_3op
10359/// Execution Slots: SLOT23
10360#[inline(always)]
10361#[cfg_attr(test, assert_instr(vlsrh))]
10362#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10363pub unsafe fn Q6_P_vlsrh_PR(rss: i64, rt: i32) -> i64 {
10364    hexagon_S2_lsr_r_vh(rss, rt)
10365}
10366
10367/// `Rdd32=vlsrw(Rss32,Rt32)`
10368///
10369/// Instruction Type: S_3op
10370/// Execution Slots: SLOT23
10371#[inline(always)]
10372#[cfg_attr(test, assert_instr(vlsrw))]
10373#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10374pub unsafe fn Q6_P_vlsrw_PR(rss: i64, rt: i32) -> i64 {
10375    hexagon_S2_lsr_r_vw(rss, rt)
10376}
10377
10378/// `Rdd32=packhl(Rs32,Rt32)`
10379///
10380/// Instruction Type: ALU32_3op
10381/// Execution Slots: SLOT0123
10382#[inline(always)]
10383#[cfg_attr(test, assert_instr(packhl))]
10384#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10385pub unsafe fn Q6_P_packhl_RR(rs: i32, rt: i32) -> i64 {
10386    hexagon_S2_packhl(rs, rt)
10387}
10388
10389/// `Rd32=parity(Rss32,Rtt32)`
10390///
10391/// Instruction Type: ALU64
10392/// Execution Slots: SLOT23
10393#[inline(always)]
10394#[cfg_attr(test, assert_instr(parity))]
10395#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10396pub unsafe fn Q6_R_parity_PP(rss: i64, rtt: i64) -> i32 {
10397    hexagon_S2_parityp(rss, rtt)
10398}
10399
10400/// `Rd32=setbit(Rs32,#u5)`
10401///
10402/// Instruction Type: S_2op
10403/// Execution Slots: SLOT23
10404#[inline(always)]
10405#[rustc_legacy_const_generics(1)]
10406#[cfg_attr(test, assert_instr(setbit, IU5 = 0))]
10407#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10408pub unsafe fn Q6_R_setbit_RI<const IU5: u32>(rs: i32) -> i32 {
10409    static_assert_uimm_bits!(IU5, 5);
10410    hexagon_S2_setbit_i(rs, IU5 as i32)
10411}
10412
10413/// `Rd32=setbit(Rs32,Rt32)`
10414///
10415/// Instruction Type: S_3op
10416/// Execution Slots: SLOT23
10417#[inline(always)]
10418#[cfg_attr(test, assert_instr(setbit))]
10419#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10420pub unsafe fn Q6_R_setbit_RR(rs: i32, rt: i32) -> i32 {
10421    hexagon_S2_setbit_r(rs, rt)
10422}
10423
10424/// `Rdd32=shuffeb(Rss32,Rtt32)`
10425///
10426/// Instruction Type: S_3op
10427/// Execution Slots: SLOT23
10428#[inline(always)]
10429#[cfg_attr(test, assert_instr(shuffeb))]
10430#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10431pub unsafe fn Q6_P_shuffeb_PP(rss: i64, rtt: i64) -> i64 {
10432    hexagon_S2_shuffeb(rss, rtt)
10433}
10434
10435/// `Rdd32=shuffeh(Rss32,Rtt32)`
10436///
10437/// Instruction Type: S_3op
10438/// Execution Slots: SLOT23
10439#[inline(always)]
10440#[cfg_attr(test, assert_instr(shuffeh))]
10441#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10442pub unsafe fn Q6_P_shuffeh_PP(rss: i64, rtt: i64) -> i64 {
10443    hexagon_S2_shuffeh(rss, rtt)
10444}
10445
10446/// `Rdd32=shuffob(Rtt32,Rss32)`
10447///
10448/// Instruction Type: S_3op
10449/// Execution Slots: SLOT23
10450#[inline(always)]
10451#[cfg_attr(test, assert_instr(shuffob))]
10452#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10453pub unsafe fn Q6_P_shuffob_PP(rtt: i64, rss: i64) -> i64 {
10454    hexagon_S2_shuffob(rtt, rss)
10455}
10456
10457/// `Rdd32=shuffoh(Rtt32,Rss32)`
10458///
10459/// Instruction Type: S_3op
10460/// Execution Slots: SLOT23
10461#[inline(always)]
10462#[cfg_attr(test, assert_instr(shuffoh))]
10463#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10464pub unsafe fn Q6_P_shuffoh_PP(rtt: i64, rss: i64) -> i64 {
10465    hexagon_S2_shuffoh(rtt, rss)
10466}
10467
10468/// `Rd32=vsathb(Rs32)`
10469///
10470/// Instruction Type: S_2op
10471/// Execution Slots: SLOT23
10472#[inline(always)]
10473#[cfg_attr(test, assert_instr(vsathb))]
10474#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10475pub unsafe fn Q6_R_vsathb_R(rs: i32) -> i32 {
10476    hexagon_S2_svsathb(rs)
10477}
10478
10479/// `Rd32=vsathub(Rs32)`
10480///
10481/// Instruction Type: S_2op
10482/// Execution Slots: SLOT23
10483#[inline(always)]
10484#[cfg_attr(test, assert_instr(vsathub))]
10485#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10486pub unsafe fn Q6_R_vsathub_R(rs: i32) -> i32 {
10487    hexagon_S2_svsathub(rs)
10488}
10489
10490/// `Rx32=tableidxb(Rs32,#u4,#U5)`
10491///
10492/// Instruction Type: S_2op
10493/// Execution Slots: SLOT0123
10494#[inline(always)]
10495#[rustc_legacy_const_generics(2, 3)]
10496#[cfg_attr(test, assert_instr(tableidxb, IU4 = 0, IU5 = 0))]
10497#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10498pub unsafe fn Q6_R_tableidxb_RII<const IU4: u32, const IU5: u32>(rx: i32, rs: i32) -> i32 {
10499    static_assert_uimm_bits!(IU4, 4);
10500    static_assert_uimm_bits!(IU5, 5);
10501    hexagon_S2_tableidxb_goodsyntax(rx, rs, IU4 as i32, IU5 as i32)
10502}
10503
10504/// `Rx32=tableidxd(Rs32,#u4,#U5)`
10505///
10506/// Instruction Type: S_2op
10507/// Execution Slots: SLOT0123
10508#[inline(always)]
10509#[rustc_legacy_const_generics(2, 3)]
10510#[cfg_attr(test, assert_instr(tableidxd, IU4 = 0, IU5 = 0))]
10511#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10512pub unsafe fn Q6_R_tableidxd_RII<const IU4: u32, const IU5: u32>(rx: i32, rs: i32) -> i32 {
10513    static_assert_uimm_bits!(IU4, 4);
10514    static_assert_uimm_bits!(IU5, 5);
10515    hexagon_S2_tableidxd_goodsyntax(rx, rs, IU4 as i32, IU5 as i32)
10516}
10517
10518/// `Rx32=tableidxh(Rs32,#u4,#U5)`
10519///
10520/// Instruction Type: S_2op
10521/// Execution Slots: SLOT0123
10522#[inline(always)]
10523#[rustc_legacy_const_generics(2, 3)]
10524#[cfg_attr(test, assert_instr(tableidxh, IU4 = 0, IU5 = 0))]
10525#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10526pub unsafe fn Q6_R_tableidxh_RII<const IU4: u32, const IU5: u32>(rx: i32, rs: i32) -> i32 {
10527    static_assert_uimm_bits!(IU4, 4);
10528    static_assert_uimm_bits!(IU5, 5);
10529    hexagon_S2_tableidxh_goodsyntax(rx, rs, IU4 as i32, IU5 as i32)
10530}
10531
10532/// `Rx32=tableidxw(Rs32,#u4,#U5)`
10533///
10534/// Instruction Type: S_2op
10535/// Execution Slots: SLOT0123
10536#[inline(always)]
10537#[rustc_legacy_const_generics(2, 3)]
10538#[cfg_attr(test, assert_instr(tableidxw, IU4 = 0, IU5 = 0))]
10539#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10540pub unsafe fn Q6_R_tableidxw_RII<const IU4: u32, const IU5: u32>(rx: i32, rs: i32) -> i32 {
10541    static_assert_uimm_bits!(IU4, 4);
10542    static_assert_uimm_bits!(IU5, 5);
10543    hexagon_S2_tableidxw_goodsyntax(rx, rs, IU4 as i32, IU5 as i32)
10544}
10545
10546/// `Rd32=togglebit(Rs32,#u5)`
10547///
10548/// Instruction Type: S_2op
10549/// Execution Slots: SLOT23
10550#[inline(always)]
10551#[rustc_legacy_const_generics(1)]
10552#[cfg_attr(test, assert_instr(togglebit, IU5 = 0))]
10553#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10554pub unsafe fn Q6_R_togglebit_RI<const IU5: u32>(rs: i32) -> i32 {
10555    static_assert_uimm_bits!(IU5, 5);
10556    hexagon_S2_togglebit_i(rs, IU5 as i32)
10557}
10558
10559/// `Rd32=togglebit(Rs32,Rt32)`
10560///
10561/// Instruction Type: S_3op
10562/// Execution Slots: SLOT23
10563#[inline(always)]
10564#[cfg_attr(test, assert_instr(togglebit))]
10565#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10566pub unsafe fn Q6_R_togglebit_RR(rs: i32, rt: i32) -> i32 {
10567    hexagon_S2_togglebit_r(rs, rt)
10568}
10569
10570/// `Pd4=tstbit(Rs32,#u5)`
10571///
10572/// Instruction Type: S_2op
10573/// Execution Slots: SLOT23
10574#[inline(always)]
10575#[rustc_legacy_const_generics(1)]
10576#[cfg_attr(test, assert_instr(tstbit, IU5 = 0))]
10577#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10578pub unsafe fn Q6_p_tstbit_RI<const IU5: u32>(rs: i32) -> i32 {
10579    static_assert_uimm_bits!(IU5, 5);
10580    hexagon_S2_tstbit_i(rs, IU5 as i32)
10581}
10582
10583/// `Pd4=tstbit(Rs32,Rt32)`
10584///
10585/// Instruction Type: S_3op
10586/// Execution Slots: SLOT23
10587#[inline(always)]
10588#[cfg_attr(test, assert_instr(tstbit))]
10589#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10590pub unsafe fn Q6_p_tstbit_RR(rs: i32, rt: i32) -> i32 {
10591    hexagon_S2_tstbit_r(rs, rt)
10592}
10593
10594/// `Rdd32=valignb(Rtt32,Rss32,#u3)`
10595///
10596/// Instruction Type: S_3op
10597/// Execution Slots: SLOT23
10598#[inline(always)]
10599#[rustc_legacy_const_generics(2)]
10600#[cfg_attr(test, assert_instr(valignb, IU3 = 0))]
10601#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10602pub unsafe fn Q6_P_valignb_PPI<const IU3: u32>(rtt: i64, rss: i64) -> i64 {
10603    static_assert_uimm_bits!(IU3, 3);
10604    hexagon_S2_valignib(rtt, rss, IU3 as i32)
10605}
10606
10607/// `Rdd32=valignb(Rtt32,Rss32,Pu4)`
10608///
10609/// Instruction Type: S_3op
10610/// Execution Slots: SLOT23
10611#[inline(always)]
10612#[cfg_attr(test, assert_instr(valignb))]
10613#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10614pub unsafe fn Q6_P_valignb_PPp(rtt: i64, rss: i64, pu: i32) -> i64 {
10615    hexagon_S2_valignrb(rtt, rss, pu)
10616}
10617
10618/// `Rdd32=vcnegh(Rss32,Rt32)`
10619///
10620/// Instruction Type: S_3op
10621/// Execution Slots: SLOT23
10622#[inline(always)]
10623#[cfg_attr(test, assert_instr(vcnegh))]
10624#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10625pub unsafe fn Q6_P_vcnegh_PR(rss: i64, rt: i32) -> i64 {
10626    hexagon_S2_vcnegh(rss, rt)
10627}
10628
10629/// `Rdd32=vcrotate(Rss32,Rt32)`
10630///
10631/// Instruction Type: S_3op
10632/// Execution Slots: SLOT23
10633#[inline(always)]
10634#[cfg_attr(test, assert_instr(vcrotate))]
10635#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10636pub unsafe fn Q6_P_vcrotate_PR(rss: i64, rt: i32) -> i64 {
10637    hexagon_S2_vcrotate(rss, rt)
10638}
10639
10640/// `Rxx32+=vrcnegh(Rss32,Rt32)`
10641///
10642/// Instruction Type: S_3op
10643/// Execution Slots: SLOT23
10644#[inline(always)]
10645#[cfg_attr(test, assert_instr(vrcnegh))]
10646#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10647pub unsafe fn Q6_P_vrcneghacc_PR(rxx: i64, rss: i64, rt: i32) -> i64 {
10648    hexagon_S2_vrcnegh(rxx, rss, rt)
10649}
10650
10651/// `Rd32=vrndwh(Rss32)`
10652///
10653/// Instruction Type: S_2op
10654/// Execution Slots: SLOT23
10655#[inline(always)]
10656#[cfg_attr(test, assert_instr(vrndwh))]
10657#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10658pub unsafe fn Q6_R_vrndwh_P(rss: i64) -> i32 {
10659    hexagon_S2_vrndpackwh(rss)
10660}
10661
10662/// `Rd32=vrndwh(Rss32):sat`
10663///
10664/// Instruction Type: S_2op
10665/// Execution Slots: SLOT23
10666#[inline(always)]
10667#[cfg_attr(test, assert_instr(vrndwh))]
10668#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10669pub unsafe fn Q6_R_vrndwh_P_sat(rss: i64) -> i32 {
10670    hexagon_S2_vrndpackwhs(rss)
10671}
10672
10673/// `Rd32=vsathb(Rss32)`
10674///
10675/// Instruction Type: S_2op
10676/// Execution Slots: SLOT23
10677#[inline(always)]
10678#[cfg_attr(test, assert_instr(vsathb))]
10679#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10680pub unsafe fn Q6_R_vsathb_P(rss: i64) -> i32 {
10681    hexagon_S2_vsathb(rss)
10682}
10683
10684/// `Rdd32=vsathb(Rss32)`
10685///
10686/// Instruction Type: S_2op
10687/// Execution Slots: SLOT23
10688#[inline(always)]
10689#[cfg_attr(test, assert_instr(vsathb))]
10690#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10691pub unsafe fn Q6_P_vsathb_P(rss: i64) -> i64 {
10692    hexagon_S2_vsathb_nopack(rss)
10693}
10694
10695/// `Rd32=vsathub(Rss32)`
10696///
10697/// Instruction Type: S_2op
10698/// Execution Slots: SLOT23
10699#[inline(always)]
10700#[cfg_attr(test, assert_instr(vsathub))]
10701#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10702pub unsafe fn Q6_R_vsathub_P(rss: i64) -> i32 {
10703    hexagon_S2_vsathub(rss)
10704}
10705
10706/// `Rdd32=vsathub(Rss32)`
10707///
10708/// Instruction Type: S_2op
10709/// Execution Slots: SLOT23
10710#[inline(always)]
10711#[cfg_attr(test, assert_instr(vsathub))]
10712#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10713pub unsafe fn Q6_P_vsathub_P(rss: i64) -> i64 {
10714    hexagon_S2_vsathub_nopack(rss)
10715}
10716
10717/// `Rd32=vsatwh(Rss32)`
10718///
10719/// Instruction Type: S_2op
10720/// Execution Slots: SLOT23
10721#[inline(always)]
10722#[cfg_attr(test, assert_instr(vsatwh))]
10723#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10724pub unsafe fn Q6_R_vsatwh_P(rss: i64) -> i32 {
10725    hexagon_S2_vsatwh(rss)
10726}
10727
10728/// `Rdd32=vsatwh(Rss32)`
10729///
10730/// Instruction Type: S_2op
10731/// Execution Slots: SLOT23
10732#[inline(always)]
10733#[cfg_attr(test, assert_instr(vsatwh))]
10734#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10735pub unsafe fn Q6_P_vsatwh_P(rss: i64) -> i64 {
10736    hexagon_S2_vsatwh_nopack(rss)
10737}
10738
10739/// `Rd32=vsatwuh(Rss32)`
10740///
10741/// Instruction Type: S_2op
10742/// Execution Slots: SLOT23
10743#[inline(always)]
10744#[cfg_attr(test, assert_instr(vsatwuh))]
10745#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10746pub unsafe fn Q6_R_vsatwuh_P(rss: i64) -> i32 {
10747    hexagon_S2_vsatwuh(rss)
10748}
10749
10750/// `Rdd32=vsatwuh(Rss32)`
10751///
10752/// Instruction Type: S_2op
10753/// Execution Slots: SLOT23
10754#[inline(always)]
10755#[cfg_attr(test, assert_instr(vsatwuh))]
10756#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10757pub unsafe fn Q6_P_vsatwuh_P(rss: i64) -> i64 {
10758    hexagon_S2_vsatwuh_nopack(rss)
10759}
10760
10761/// `Rd32=vsplatb(Rs32)`
10762///
10763/// Instruction Type: S_2op
10764/// Execution Slots: SLOT23
10765#[inline(always)]
10766#[cfg_attr(test, assert_instr(vsplatb))]
10767#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10768pub unsafe fn Q6_R_vsplatb_R(rs: i32) -> i32 {
10769    hexagon_S2_vsplatrb(rs)
10770}
10771
10772/// `Rdd32=vsplath(Rs32)`
10773///
10774/// Instruction Type: S_2op
10775/// Execution Slots: SLOT23
10776#[inline(always)]
10777#[cfg_attr(test, assert_instr(vsplath))]
10778#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10779pub unsafe fn Q6_P_vsplath_R(rs: i32) -> i64 {
10780    hexagon_S2_vsplatrh(rs)
10781}
10782
10783/// `Rdd32=vspliceb(Rss32,Rtt32,#u3)`
10784///
10785/// Instruction Type: S_3op
10786/// Execution Slots: SLOT23
10787#[inline(always)]
10788#[rustc_legacy_const_generics(2)]
10789#[cfg_attr(test, assert_instr(vspliceb, IU3 = 0))]
10790#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10791pub unsafe fn Q6_P_vspliceb_PPI<const IU3: u32>(rss: i64, rtt: i64) -> i64 {
10792    static_assert_uimm_bits!(IU3, 3);
10793    hexagon_S2_vspliceib(rss, rtt, IU3 as i32)
10794}
10795
10796/// `Rdd32=vspliceb(Rss32,Rtt32,Pu4)`
10797///
10798/// Instruction Type: S_3op
10799/// Execution Slots: SLOT23
10800#[inline(always)]
10801#[cfg_attr(test, assert_instr(vspliceb))]
10802#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10803pub unsafe fn Q6_P_vspliceb_PPp(rss: i64, rtt: i64, pu: i32) -> i64 {
10804    hexagon_S2_vsplicerb(rss, rtt, pu)
10805}
10806
10807/// `Rdd32=vsxtbh(Rs32)`
10808///
10809/// Instruction Type: S_2op
10810/// Execution Slots: SLOT23
10811#[inline(always)]
10812#[cfg_attr(test, assert_instr(vsxtbh))]
10813#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10814pub unsafe fn Q6_P_vsxtbh_R(rs: i32) -> i64 {
10815    hexagon_S2_vsxtbh(rs)
10816}
10817
10818/// `Rdd32=vsxthw(Rs32)`
10819///
10820/// Instruction Type: S_2op
10821/// Execution Slots: SLOT23
10822#[inline(always)]
10823#[cfg_attr(test, assert_instr(vsxthw))]
10824#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10825pub unsafe fn Q6_P_vsxthw_R(rs: i32) -> i64 {
10826    hexagon_S2_vsxthw(rs)
10827}
10828
10829/// `Rd32=vtrunehb(Rss32)`
10830///
10831/// Instruction Type: S_2op
10832/// Execution Slots: SLOT23
10833#[inline(always)]
10834#[cfg_attr(test, assert_instr(vtrunehb))]
10835#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10836pub unsafe fn Q6_R_vtrunehb_P(rss: i64) -> i32 {
10837    hexagon_S2_vtrunehb(rss)
10838}
10839
10840/// `Rdd32=vtrunewh(Rss32,Rtt32)`
10841///
10842/// Instruction Type: S_3op
10843/// Execution Slots: SLOT23
10844#[inline(always)]
10845#[cfg_attr(test, assert_instr(vtrunewh))]
10846#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10847pub unsafe fn Q6_P_vtrunewh_PP(rss: i64, rtt: i64) -> i64 {
10848    hexagon_S2_vtrunewh(rss, rtt)
10849}
10850
10851/// `Rd32=vtrunohb(Rss32)`
10852///
10853/// Instruction Type: S_2op
10854/// Execution Slots: SLOT23
10855#[inline(always)]
10856#[cfg_attr(test, assert_instr(vtrunohb))]
10857#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10858pub unsafe fn Q6_R_vtrunohb_P(rss: i64) -> i32 {
10859    hexagon_S2_vtrunohb(rss)
10860}
10861
10862/// `Rdd32=vtrunowh(Rss32,Rtt32)`
10863///
10864/// Instruction Type: S_3op
10865/// Execution Slots: SLOT23
10866#[inline(always)]
10867#[cfg_attr(test, assert_instr(vtrunowh))]
10868#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10869pub unsafe fn Q6_P_vtrunowh_PP(rss: i64, rtt: i64) -> i64 {
10870    hexagon_S2_vtrunowh(rss, rtt)
10871}
10872
10873/// `Rdd32=vzxtbh(Rs32)`
10874///
10875/// Instruction Type: S_2op
10876/// Execution Slots: SLOT23
10877#[inline(always)]
10878#[cfg_attr(test, assert_instr(vzxtbh))]
10879#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10880pub unsafe fn Q6_P_vzxtbh_R(rs: i32) -> i64 {
10881    hexagon_S2_vzxtbh(rs)
10882}
10883
10884/// `Rdd32=vzxthw(Rs32)`
10885///
10886/// Instruction Type: S_2op
10887/// Execution Slots: SLOT23
10888#[inline(always)]
10889#[cfg_attr(test, assert_instr(vzxthw))]
10890#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10891pub unsafe fn Q6_P_vzxthw_R(rs: i32) -> i64 {
10892    hexagon_S2_vzxthw(rs)
10893}
10894
10895/// `Rd32=add(Rs32,add(Ru32,#s6))`
10896///
10897/// Instruction Type: ALU64
10898/// Execution Slots: SLOT23
10899#[inline(always)]
10900#[rustc_legacy_const_generics(2)]
10901#[cfg_attr(test, assert_instr(add, IS6 = 0))]
10902#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10903pub unsafe fn Q6_R_add_add_RRI<const IS6: i32>(rs: i32, ru: i32) -> i32 {
10904    static_assert_simm_bits!(IS6, 6);
10905    hexagon_S4_addaddi(rs, ru, IS6)
10906}
10907
10908/// `Rx32=add(#u8,asl(Rx32,#U5))`
10909///
10910/// Instruction Type: ALU64
10911/// Execution Slots: SLOT23
10912#[inline(always)]
10913#[rustc_legacy_const_generics(0, 2)]
10914#[cfg_attr(test, assert_instr(add, IU8 = 0, IU5 = 0))]
10915#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10916pub unsafe fn Q6_R_add_asl_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
10917    static_assert_uimm_bits!(IU8, 8);
10918    static_assert_uimm_bits!(IU5, 5);
10919    hexagon_S4_addi_asl_ri(IU8 as i32, rx, IU5 as i32)
10920}
10921
10922/// `Rx32=add(#u8,lsr(Rx32,#U5))`
10923///
10924/// Instruction Type: ALU64
10925/// Execution Slots: SLOT23
10926#[inline(always)]
10927#[rustc_legacy_const_generics(0, 2)]
10928#[cfg_attr(test, assert_instr(add, IU8 = 0, IU5 = 0))]
10929#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10930pub unsafe fn Q6_R_add_lsr_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
10931    static_assert_uimm_bits!(IU8, 8);
10932    static_assert_uimm_bits!(IU5, 5);
10933    hexagon_S4_addi_lsr_ri(IU8 as i32, rx, IU5 as i32)
10934}
10935
10936/// `Rx32=and(#u8,asl(Rx32,#U5))`
10937///
10938/// Instruction Type: ALU64
10939/// Execution Slots: SLOT23
10940#[inline(always)]
10941#[rustc_legacy_const_generics(0, 2)]
10942#[cfg_attr(test, assert_instr(and, IU8 = 0, IU5 = 0))]
10943#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10944pub unsafe fn Q6_R_and_asl_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
10945    static_assert_uimm_bits!(IU8, 8);
10946    static_assert_uimm_bits!(IU5, 5);
10947    hexagon_S4_andi_asl_ri(IU8 as i32, rx, IU5 as i32)
10948}
10949
10950/// `Rx32=and(#u8,lsr(Rx32,#U5))`
10951///
10952/// Instruction Type: ALU64
10953/// Execution Slots: SLOT23
10954#[inline(always)]
10955#[rustc_legacy_const_generics(0, 2)]
10956#[cfg_attr(test, assert_instr(and, IU8 = 0, IU5 = 0))]
10957#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10958pub unsafe fn Q6_R_and_lsr_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
10959    static_assert_uimm_bits!(IU8, 8);
10960    static_assert_uimm_bits!(IU5, 5);
10961    hexagon_S4_andi_lsr_ri(IU8 as i32, rx, IU5 as i32)
10962}
10963
10964/// `Rd32=add(clb(Rs32),#s6)`
10965///
10966/// Instruction Type: S_2op
10967/// Execution Slots: SLOT23
10968#[inline(always)]
10969#[rustc_legacy_const_generics(1)]
10970#[cfg_attr(test, assert_instr(add, IS6 = 0))]
10971#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10972pub unsafe fn Q6_R_add_clb_RI<const IS6: i32>(rs: i32) -> i32 {
10973    static_assert_simm_bits!(IS6, 6);
10974    hexagon_S4_clbaddi(rs, IS6)
10975}
10976
10977/// `Rd32=add(clb(Rss32),#s6)`
10978///
10979/// Instruction Type: S_2op
10980/// Execution Slots: SLOT23
10981#[inline(always)]
10982#[rustc_legacy_const_generics(1)]
10983#[cfg_attr(test, assert_instr(add, IS6 = 0))]
10984#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10985pub unsafe fn Q6_R_add_clb_PI<const IS6: i32>(rss: i64) -> i32 {
10986    static_assert_simm_bits!(IS6, 6);
10987    hexagon_S4_clbpaddi(rss, IS6)
10988}
10989
10990/// `Rd32=normamt(Rss32)`
10991///
10992/// Instruction Type: S_2op
10993/// Execution Slots: SLOT23
10994#[inline(always)]
10995#[cfg_attr(test, assert_instr(normamt))]
10996#[unstable(feature = "stdarch_hexagon", issue = "151523")]
10997pub unsafe fn Q6_R_normamt_P(rss: i64) -> i32 {
10998    hexagon_S4_clbpnorm(rss)
10999}
11000
11001/// `Rd32=extract(Rs32,#u5,#U5)`
11002///
11003/// Instruction Type: S_2op
11004/// Execution Slots: SLOT23
11005#[inline(always)]
11006#[rustc_legacy_const_generics(1, 2)]
11007#[cfg_attr(test, assert_instr(extract, IU5 = 0, IU5_2 = 0))]
11008#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11009pub unsafe fn Q6_R_extract_RII<const IU5: u32, const IU5_2: u32>(rs: i32) -> i32 {
11010    static_assert_uimm_bits!(IU5, 5);
11011    static_assert_uimm_bits!(IU5_2, 5);
11012    hexagon_S4_extract(rs, IU5 as i32, IU5_2 as i32)
11013}
11014
11015/// `Rd32=extract(Rs32,Rtt32)`
11016///
11017/// Instruction Type: S_3op
11018/// Execution Slots: SLOT23
11019#[inline(always)]
11020#[cfg_attr(test, assert_instr(extract))]
11021#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11022pub unsafe fn Q6_R_extract_RP(rs: i32, rtt: i64) -> i32 {
11023    hexagon_S4_extract_rp(rs, rtt)
11024}
11025
11026/// `Rdd32=extract(Rss32,#u6,#U6)`
11027///
11028/// Instruction Type: S_2op
11029/// Execution Slots: SLOT23
11030#[inline(always)]
11031#[rustc_legacy_const_generics(1, 2)]
11032#[cfg_attr(test, assert_instr(extract, IU6 = 0, IU6_2 = 0))]
11033#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11034pub unsafe fn Q6_P_extract_PII<const IU6: u32, const IU6_2: u32>(rss: i64) -> i64 {
11035    static_assert_uimm_bits!(IU6, 6);
11036    static_assert_uimm_bits!(IU6_2, 6);
11037    hexagon_S4_extractp(rss, IU6 as i32, IU6_2 as i32)
11038}
11039
11040/// `Rdd32=extract(Rss32,Rtt32)`
11041///
11042/// Instruction Type: S_3op
11043/// Execution Slots: SLOT23
11044#[inline(always)]
11045#[cfg_attr(test, assert_instr(extract))]
11046#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11047pub unsafe fn Q6_P_extract_PP(rss: i64, rtt: i64) -> i64 {
11048    hexagon_S4_extractp_rp(rss, rtt)
11049}
11050
11051/// `Rd32=lsl(#s6,Rt32)`
11052///
11053/// Instruction Type: S_3op
11054/// Execution Slots: SLOT23
11055#[inline(always)]
11056#[rustc_legacy_const_generics(0)]
11057#[cfg_attr(test, assert_instr(lsl, IS6 = 0))]
11058#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11059pub unsafe fn Q6_R_lsl_IR<const IS6: i32>(rt: i32) -> i32 {
11060    static_assert_simm_bits!(IS6, 6);
11061    hexagon_S4_lsli(IS6, rt)
11062}
11063
11064/// `Pd4=!tstbit(Rs32,#u5)`
11065///
11066/// Instruction Type: S_2op
11067/// Execution Slots: SLOT23
11068#[inline(always)]
11069#[rustc_legacy_const_generics(1)]
11070#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11071pub unsafe fn Q6_p_not_tstbit_RI<const IU5: u32>(rs: i32) -> i32 {
11072    static_assert_uimm_bits!(IU5, 5);
11073    hexagon_S4_ntstbit_i(rs, IU5 as i32)
11074}
11075
11076/// `Pd4=!tstbit(Rs32,Rt32)`
11077///
11078/// Instruction Type: S_3op
11079/// Execution Slots: SLOT23
11080#[inline(always)]
11081#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11082pub unsafe fn Q6_p_not_tstbit_RR(rs: i32, rt: i32) -> i32 {
11083    hexagon_S4_ntstbit_r(rs, rt)
11084}
11085
11086/// `Rx32|=and(Rs32,#s10)`
11087///
11088/// Instruction Type: ALU64
11089/// Execution Slots: SLOT23
11090#[inline(always)]
11091#[rustc_legacy_const_generics(2)]
11092#[cfg_attr(test, assert_instr(and, IS10 = 0))]
11093#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11094pub unsafe fn Q6_R_andor_RI<const IS10: i32>(rx: i32, rs: i32) -> i32 {
11095    static_assert_simm_bits!(IS10, 10);
11096    hexagon_S4_or_andi(rx, rs, IS10)
11097}
11098
11099/// `Rx32=or(Ru32,and(Rx32,#s10))`
11100///
11101/// Instruction Type: ALU64
11102/// Execution Slots: SLOT23
11103#[inline(always)]
11104#[rustc_legacy_const_generics(2)]
11105#[cfg_attr(test, assert_instr(or, IS10 = 0))]
11106#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11107pub unsafe fn Q6_R_or_and_RRI<const IS10: i32>(ru: i32, rx: i32) -> i32 {
11108    static_assert_simm_bits!(IS10, 10);
11109    hexagon_S4_or_andix(ru, rx, IS10)
11110}
11111
11112/// `Rx32|=or(Rs32,#s10)`
11113///
11114/// Instruction Type: ALU64
11115/// Execution Slots: SLOT23
11116#[inline(always)]
11117#[rustc_legacy_const_generics(2)]
11118#[cfg_attr(test, assert_instr(or, IS10 = 0))]
11119#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11120pub unsafe fn Q6_R_oror_RI<const IS10: i32>(rx: i32, rs: i32) -> i32 {
11121    static_assert_simm_bits!(IS10, 10);
11122    hexagon_S4_or_ori(rx, rs, IS10)
11123}
11124
11125/// `Rx32=or(#u8,asl(Rx32,#U5))`
11126///
11127/// Instruction Type: ALU64
11128/// Execution Slots: SLOT23
11129#[inline(always)]
11130#[rustc_legacy_const_generics(0, 2)]
11131#[cfg_attr(test, assert_instr(or, IU8 = 0, IU5 = 0))]
11132#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11133pub unsafe fn Q6_R_or_asl_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
11134    static_assert_uimm_bits!(IU8, 8);
11135    static_assert_uimm_bits!(IU5, 5);
11136    hexagon_S4_ori_asl_ri(IU8 as i32, rx, IU5 as i32)
11137}
11138
11139/// `Rx32=or(#u8,lsr(Rx32,#U5))`
11140///
11141/// Instruction Type: ALU64
11142/// Execution Slots: SLOT23
11143#[inline(always)]
11144#[rustc_legacy_const_generics(0, 2)]
11145#[cfg_attr(test, assert_instr(or, IU8 = 0, IU5 = 0))]
11146#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11147pub unsafe fn Q6_R_or_lsr_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
11148    static_assert_uimm_bits!(IU8, 8);
11149    static_assert_uimm_bits!(IU5, 5);
11150    hexagon_S4_ori_lsr_ri(IU8 as i32, rx, IU5 as i32)
11151}
11152
11153/// `Rd32=parity(Rs32,Rt32)`
11154///
11155/// Instruction Type: ALU64
11156/// Execution Slots: SLOT23
11157#[inline(always)]
11158#[cfg_attr(test, assert_instr(parity))]
11159#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11160pub unsafe fn Q6_R_parity_RR(rs: i32, rt: i32) -> i32 {
11161    hexagon_S4_parity(rs, rt)
11162}
11163
11164/// `Rd32=add(Rs32,sub(#s6,Ru32))`
11165///
11166/// Instruction Type: ALU64
11167/// Execution Slots: SLOT23
11168#[inline(always)]
11169#[rustc_legacy_const_generics(1)]
11170#[cfg_attr(test, assert_instr(add, IS6 = 0))]
11171#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11172pub unsafe fn Q6_R_add_sub_RIR<const IS6: i32>(rs: i32, ru: i32) -> i32 {
11173    static_assert_simm_bits!(IS6, 6);
11174    hexagon_S4_subaddi(rs, IS6, ru)
11175}
11176
11177/// `Rx32=sub(#u8,asl(Rx32,#U5))`
11178///
11179/// Instruction Type: ALU64
11180/// Execution Slots: SLOT23
11181#[inline(always)]
11182#[rustc_legacy_const_generics(0, 2)]
11183#[cfg_attr(test, assert_instr(sub, IU8 = 0, IU5 = 0))]
11184#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11185pub unsafe fn Q6_R_sub_asl_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
11186    static_assert_uimm_bits!(IU8, 8);
11187    static_assert_uimm_bits!(IU5, 5);
11188    hexagon_S4_subi_asl_ri(IU8 as i32, rx, IU5 as i32)
11189}
11190
11191/// `Rx32=sub(#u8,lsr(Rx32,#U5))`
11192///
11193/// Instruction Type: ALU64
11194/// Execution Slots: SLOT23
11195#[inline(always)]
11196#[rustc_legacy_const_generics(0, 2)]
11197#[cfg_attr(test, assert_instr(sub, IU8 = 0, IU5 = 0))]
11198#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11199pub unsafe fn Q6_R_sub_lsr_IRI<const IU8: u32, const IU5: u32>(rx: i32) -> i32 {
11200    static_assert_uimm_bits!(IU8, 8);
11201    static_assert_uimm_bits!(IU5, 5);
11202    hexagon_S4_subi_lsr_ri(IU8 as i32, rx, IU5 as i32)
11203}
11204
11205/// `Rdd32=vrcrotate(Rss32,Rt32,#u2)`
11206///
11207/// Instruction Type: S_3op
11208/// Execution Slots: SLOT23
11209#[inline(always)]
11210#[rustc_legacy_const_generics(2)]
11211#[cfg_attr(test, assert_instr(vrcrotate, IU2 = 0))]
11212#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11213pub unsafe fn Q6_P_vrcrotate_PRI<const IU2: u32>(rss: i64, rt: i32) -> i64 {
11214    static_assert_uimm_bits!(IU2, 2);
11215    hexagon_S4_vrcrotate(rss, rt, IU2 as i32)
11216}
11217
11218/// `Rxx32+=vrcrotate(Rss32,Rt32,#u2)`
11219///
11220/// Instruction Type: S_3op
11221/// Execution Slots: SLOT23
11222#[inline(always)]
11223#[rustc_legacy_const_generics(3)]
11224#[cfg_attr(test, assert_instr(vrcrotate, IU2 = 0))]
11225#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11226pub unsafe fn Q6_P_vrcrotateacc_PRI<const IU2: u32>(rxx: i64, rss: i64, rt: i32) -> i64 {
11227    static_assert_uimm_bits!(IU2, 2);
11228    hexagon_S4_vrcrotate_acc(rxx, rss, rt, IU2 as i32)
11229}
11230
11231/// `Rdd32=vxaddsubh(Rss32,Rtt32):sat`
11232///
11233/// Instruction Type: S_3op
11234/// Execution Slots: SLOT23
11235#[inline(always)]
11236#[cfg_attr(test, assert_instr(vxaddsubh))]
11237#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11238pub unsafe fn Q6_P_vxaddsubh_PP_sat(rss: i64, rtt: i64) -> i64 {
11239    hexagon_S4_vxaddsubh(rss, rtt)
11240}
11241
11242/// `Rdd32=vxaddsubh(Rss32,Rtt32):rnd:>>1:sat`
11243///
11244/// Instruction Type: S_3op
11245/// Execution Slots: SLOT23
11246#[inline(always)]
11247#[cfg_attr(test, assert_instr(vxaddsubh))]
11248#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11249pub unsafe fn Q6_P_vxaddsubh_PP_rnd_rs1_sat(rss: i64, rtt: i64) -> i64 {
11250    hexagon_S4_vxaddsubhr(rss, rtt)
11251}
11252
11253/// `Rdd32=vxaddsubw(Rss32,Rtt32):sat`
11254///
11255/// Instruction Type: S_3op
11256/// Execution Slots: SLOT23
11257#[inline(always)]
11258#[cfg_attr(test, assert_instr(vxaddsubw))]
11259#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11260pub unsafe fn Q6_P_vxaddsubw_PP_sat(rss: i64, rtt: i64) -> i64 {
11261    hexagon_S4_vxaddsubw(rss, rtt)
11262}
11263
11264/// `Rdd32=vxsubaddh(Rss32,Rtt32):sat`
11265///
11266/// Instruction Type: S_3op
11267/// Execution Slots: SLOT23
11268#[inline(always)]
11269#[cfg_attr(test, assert_instr(vxsubaddh))]
11270#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11271pub unsafe fn Q6_P_vxsubaddh_PP_sat(rss: i64, rtt: i64) -> i64 {
11272    hexagon_S4_vxsubaddh(rss, rtt)
11273}
11274
11275/// `Rdd32=vxsubaddh(Rss32,Rtt32):rnd:>>1:sat`
11276///
11277/// Instruction Type: S_3op
11278/// Execution Slots: SLOT23
11279#[inline(always)]
11280#[cfg_attr(test, assert_instr(vxsubaddh))]
11281#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11282pub unsafe fn Q6_P_vxsubaddh_PP_rnd_rs1_sat(rss: i64, rtt: i64) -> i64 {
11283    hexagon_S4_vxsubaddhr(rss, rtt)
11284}
11285
11286/// `Rdd32=vxsubaddw(Rss32,Rtt32):sat`
11287///
11288/// Instruction Type: S_3op
11289/// Execution Slots: SLOT23
11290#[inline(always)]
11291#[cfg_attr(test, assert_instr(vxsubaddw))]
11292#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11293pub unsafe fn Q6_P_vxsubaddw_PP_sat(rss: i64, rtt: i64) -> i64 {
11294    hexagon_S4_vxsubaddw(rss, rtt)
11295}
11296
11297/// `Rd32=vasrhub(Rss32,#u4):rnd:sat`
11298///
11299/// Instruction Type: S_2op
11300/// Execution Slots: SLOT0123
11301#[inline(always)]
11302#[rustc_legacy_const_generics(1)]
11303#[cfg_attr(test, assert_instr(vasrhub, IU4 = 0))]
11304#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11305pub unsafe fn Q6_R_vasrhub_PI_rnd_sat<const IU4: u32>(rss: i64) -> i32 {
11306    static_assert_uimm_bits!(IU4, 4);
11307    hexagon_S5_asrhub_rnd_sat_goodsyntax(rss, IU4 as i32)
11308}
11309
11310/// `Rd32=vasrhub(Rss32,#u4):sat`
11311///
11312/// Instruction Type: S_2op
11313/// Execution Slots: SLOT23
11314#[inline(always)]
11315#[rustc_legacy_const_generics(1)]
11316#[cfg_attr(test, assert_instr(vasrhub, IU4 = 0))]
11317#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11318pub unsafe fn Q6_R_vasrhub_PI_sat<const IU4: u32>(rss: i64) -> i32 {
11319    static_assert_uimm_bits!(IU4, 4);
11320    hexagon_S5_asrhub_sat(rss, IU4 as i32)
11321}
11322
11323/// `Rd32=popcount(Rss32)`
11324///
11325/// Instruction Type: S_2op
11326/// Execution Slots: SLOT23
11327#[inline(always)]
11328#[cfg_attr(test, assert_instr(popcount))]
11329#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11330pub unsafe fn Q6_R_popcount_P(rss: i64) -> i32 {
11331    hexagon_S5_popcountp(rss)
11332}
11333
11334/// `Rdd32=vasrh(Rss32,#u4):rnd`
11335///
11336/// Instruction Type: S_2op
11337/// Execution Slots: SLOT0123
11338#[inline(always)]
11339#[rustc_legacy_const_generics(1)]
11340#[cfg_attr(test, assert_instr(vasrh, IU4 = 0))]
11341#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11342pub unsafe fn Q6_P_vasrh_PI_rnd<const IU4: u32>(rss: i64) -> i64 {
11343    static_assert_uimm_bits!(IU4, 4);
11344    hexagon_S5_vasrhrnd_goodsyntax(rss, IU4 as i32)
11345}
11346
11347/// `dccleana(Rs32)`
11348///
11349/// Instruction Type: ST
11350/// Execution Slots: SLOT0
11351#[inline(always)]
11352#[cfg_attr(test, assert_instr(dccleana))]
11353#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11354pub unsafe fn Q6_dccleana_A(rs: i32) {
11355    hexagon_Y2_dccleana(rs)
11356}
11357
11358/// `dccleaninva(Rs32)`
11359///
11360/// Instruction Type: ST
11361/// Execution Slots: SLOT0
11362#[inline(always)]
11363#[cfg_attr(test, assert_instr(dccleaninva))]
11364#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11365pub unsafe fn Q6_dccleaninva_A(rs: i32) {
11366    hexagon_Y2_dccleaninva(rs)
11367}
11368
11369/// `dcfetch(Rs32)`
11370///
11371/// Instruction Type: MAPPING
11372/// Execution Slots: SLOT0123
11373#[inline(always)]
11374#[cfg_attr(test, assert_instr(dcfetch))]
11375#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11376pub unsafe fn Q6_dcfetch_A(rs: i32) {
11377    hexagon_Y2_dcfetch(rs)
11378}
11379
11380/// `dcinva(Rs32)`
11381///
11382/// Instruction Type: ST
11383/// Execution Slots: SLOT0
11384#[inline(always)]
11385#[cfg_attr(test, assert_instr(dcinva))]
11386#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11387pub unsafe fn Q6_dcinva_A(rs: i32) {
11388    hexagon_Y2_dcinva(rs)
11389}
11390
11391/// `dczeroa(Rs32)`
11392///
11393/// Instruction Type: ST
11394/// Execution Slots: SLOT0
11395#[inline(always)]
11396#[cfg_attr(test, assert_instr(dczeroa))]
11397#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11398pub unsafe fn Q6_dczeroa_A(rs: i32) {
11399    hexagon_Y2_dczeroa(rs)
11400}
11401
11402/// `l2fetch(Rs32,Rt32)`
11403///
11404/// Instruction Type: ST
11405/// Execution Slots: SLOT0
11406#[inline(always)]
11407#[cfg_attr(test, assert_instr(l2fetch))]
11408#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11409pub unsafe fn Q6_l2fetch_AR(rs: i32, rt: i32) {
11410    hexagon_Y4_l2fetch(rs, rt)
11411}
11412
11413/// `l2fetch(Rs32,Rtt32)`
11414///
11415/// Instruction Type: ST
11416/// Execution Slots: SLOT0
11417#[inline(always)]
11418#[cfg_attr(test, assert_instr(l2fetch))]
11419#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11420pub unsafe fn Q6_l2fetch_AP(rs: i32, rtt: i64) {
11421    hexagon_Y5_l2fetch(rs, rtt)
11422}
11423
11424/// `Rdd32=rol(Rss32,#u6)`
11425///
11426/// Instruction Type: S_2op
11427/// Execution Slots: SLOT23
11428/// Requires: V60
11429#[inline]
11430#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11431#[rustc_legacy_const_generics(1)]
11432#[cfg_attr(test, assert_instr(rol, IU6 = 0))]
11433#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11434pub unsafe fn Q6_P_rol_PI<const IU6: u32>(rss: i64) -> i64 {
11435    static_assert_uimm_bits!(IU6, 6);
11436    hexagon_S6_rol_i_p(rss, IU6 as i32)
11437}
11438
11439/// `Rxx32+=rol(Rss32,#u6)`
11440///
11441/// Instruction Type: S_2op
11442/// Execution Slots: SLOT23
11443/// Requires: V60
11444#[inline]
11445#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11446#[rustc_legacy_const_generics(2)]
11447#[cfg_attr(test, assert_instr(rol, IU6 = 0))]
11448#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11449pub unsafe fn Q6_P_rolacc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
11450    static_assert_uimm_bits!(IU6, 6);
11451    hexagon_S6_rol_i_p_acc(rxx, rss, IU6 as i32)
11452}
11453
11454/// `Rxx32&=rol(Rss32,#u6)`
11455///
11456/// Instruction Type: S_2op
11457/// Execution Slots: SLOT23
11458/// Requires: V60
11459#[inline]
11460#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11461#[rustc_legacy_const_generics(2)]
11462#[cfg_attr(test, assert_instr(rol, IU6 = 0))]
11463#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11464pub unsafe fn Q6_P_roland_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
11465    static_assert_uimm_bits!(IU6, 6);
11466    hexagon_S6_rol_i_p_and(rxx, rss, IU6 as i32)
11467}
11468
11469/// `Rxx32-=rol(Rss32,#u6)`
11470///
11471/// Instruction Type: S_2op
11472/// Execution Slots: SLOT23
11473/// Requires: V60
11474#[inline]
11475#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11476#[rustc_legacy_const_generics(2)]
11477#[cfg_attr(test, assert_instr(rol, IU6 = 0))]
11478#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11479pub unsafe fn Q6_P_rolnac_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
11480    static_assert_uimm_bits!(IU6, 6);
11481    hexagon_S6_rol_i_p_nac(rxx, rss, IU6 as i32)
11482}
11483
11484/// `Rxx32|=rol(Rss32,#u6)`
11485///
11486/// Instruction Type: S_2op
11487/// Execution Slots: SLOT23
11488/// Requires: V60
11489#[inline]
11490#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11491#[rustc_legacy_const_generics(2)]
11492#[cfg_attr(test, assert_instr(rol, IU6 = 0))]
11493#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11494pub unsafe fn Q6_P_rolor_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
11495    static_assert_uimm_bits!(IU6, 6);
11496    hexagon_S6_rol_i_p_or(rxx, rss, IU6 as i32)
11497}
11498
11499/// `Rxx32^=rol(Rss32,#u6)`
11500///
11501/// Instruction Type: S_2op
11502/// Execution Slots: SLOT23
11503/// Requires: V60
11504#[inline]
11505#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11506#[rustc_legacy_const_generics(2)]
11507#[cfg_attr(test, assert_instr(rol, IU6 = 0))]
11508#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11509pub unsafe fn Q6_P_rolxacc_PI<const IU6: u32>(rxx: i64, rss: i64) -> i64 {
11510    static_assert_uimm_bits!(IU6, 6);
11511    hexagon_S6_rol_i_p_xacc(rxx, rss, IU6 as i32)
11512}
11513
11514/// `Rd32=rol(Rs32,#u5)`
11515///
11516/// Instruction Type: S_2op
11517/// Execution Slots: SLOT23
11518/// Requires: V60
11519#[inline]
11520#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11521#[rustc_legacy_const_generics(1)]
11522#[cfg_attr(test, assert_instr(rol, IU5 = 0))]
11523#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11524pub unsafe fn Q6_R_rol_RI<const IU5: u32>(rs: i32) -> i32 {
11525    static_assert_uimm_bits!(IU5, 5);
11526    hexagon_S6_rol_i_r(rs, IU5 as i32)
11527}
11528
11529/// `Rx32+=rol(Rs32,#u5)`
11530///
11531/// Instruction Type: S_2op
11532/// Execution Slots: SLOT23
11533/// Requires: V60
11534#[inline]
11535#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11536#[rustc_legacy_const_generics(2)]
11537#[cfg_attr(test, assert_instr(rol, IU5 = 0))]
11538#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11539pub unsafe fn Q6_R_rolacc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
11540    static_assert_uimm_bits!(IU5, 5);
11541    hexagon_S6_rol_i_r_acc(rx, rs, IU5 as i32)
11542}
11543
11544/// `Rx32&=rol(Rs32,#u5)`
11545///
11546/// Instruction Type: S_2op
11547/// Execution Slots: SLOT23
11548/// Requires: V60
11549#[inline]
11550#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11551#[rustc_legacy_const_generics(2)]
11552#[cfg_attr(test, assert_instr(rol, IU5 = 0))]
11553#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11554pub unsafe fn Q6_R_roland_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
11555    static_assert_uimm_bits!(IU5, 5);
11556    hexagon_S6_rol_i_r_and(rx, rs, IU5 as i32)
11557}
11558
11559/// `Rx32-=rol(Rs32,#u5)`
11560///
11561/// Instruction Type: S_2op
11562/// Execution Slots: SLOT23
11563/// Requires: V60
11564#[inline]
11565#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11566#[rustc_legacy_const_generics(2)]
11567#[cfg_attr(test, assert_instr(rol, IU5 = 0))]
11568#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11569pub unsafe fn Q6_R_rolnac_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
11570    static_assert_uimm_bits!(IU5, 5);
11571    hexagon_S6_rol_i_r_nac(rx, rs, IU5 as i32)
11572}
11573
11574/// `Rx32|=rol(Rs32,#u5)`
11575///
11576/// Instruction Type: S_2op
11577/// Execution Slots: SLOT23
11578/// Requires: V60
11579#[inline]
11580#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11581#[rustc_legacy_const_generics(2)]
11582#[cfg_attr(test, assert_instr(rol, IU5 = 0))]
11583#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11584pub unsafe fn Q6_R_rolor_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
11585    static_assert_uimm_bits!(IU5, 5);
11586    hexagon_S6_rol_i_r_or(rx, rs, IU5 as i32)
11587}
11588
11589/// `Rx32^=rol(Rs32,#u5)`
11590///
11591/// Instruction Type: S_2op
11592/// Execution Slots: SLOT23
11593/// Requires: V60
11594#[inline]
11595#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))]
11596#[rustc_legacy_const_generics(2)]
11597#[cfg_attr(test, assert_instr(rol, IU5 = 0))]
11598#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11599pub unsafe fn Q6_R_rolxacc_RI<const IU5: u32>(rx: i32, rs: i32) -> i32 {
11600    static_assert_uimm_bits!(IU5, 5);
11601    hexagon_S6_rol_i_r_xacc(rx, rs, IU5 as i32)
11602}
11603
11604/// `Rdd32=vabsdiffb(Rtt32,Rss32)`
11605///
11606/// Instruction Type: M
11607/// Execution Slots: SLOT23
11608/// Requires: V62
11609#[inline]
11610#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))]
11611#[cfg_attr(test, assert_instr(vabsdiffb))]
11612#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11613pub unsafe fn Q6_P_vabsdiffb_PP(rtt: i64, rss: i64) -> i64 {
11614    hexagon_M6_vabsdiffb(rtt, rss)
11615}
11616
11617/// `Rdd32=vabsdiffub(Rtt32,Rss32)`
11618///
11619/// Instruction Type: M
11620/// Execution Slots: SLOT23
11621/// Requires: V62
11622#[inline]
11623#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))]
11624#[cfg_attr(test, assert_instr(vabsdiffub))]
11625#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11626pub unsafe fn Q6_P_vabsdiffub_PP(rtt: i64, rss: i64) -> i64 {
11627    hexagon_M6_vabsdiffub(rtt, rss)
11628}
11629
11630/// `Rdd32=vsplatb(Rs32)`
11631///
11632/// Instruction Type: S_2op
11633/// Execution Slots: SLOT23
11634/// Requires: V62
11635#[inline]
11636#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))]
11637#[cfg_attr(test, assert_instr(vsplatb))]
11638#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11639pub unsafe fn Q6_P_vsplatb_R(rs: i32) -> i64 {
11640    hexagon_S6_vsplatrbp(rs)
11641}
11642
11643/// `Rdd32=vtrunehb(Rss32,Rtt32)`
11644///
11645/// Instruction Type: S_3op
11646/// Execution Slots: SLOT23
11647/// Requires: V62
11648#[inline]
11649#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))]
11650#[cfg_attr(test, assert_instr(vtrunehb))]
11651#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11652pub unsafe fn Q6_P_vtrunehb_PP(rss: i64, rtt: i64) -> i64 {
11653    hexagon_S6_vtrunehb_ppp(rss, rtt)
11654}
11655
11656/// `Rdd32=vtrunohb(Rss32,Rtt32)`
11657///
11658/// Instruction Type: S_3op
11659/// Execution Slots: SLOT23
11660/// Requires: V62
11661#[inline]
11662#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v62"))]
11663#[cfg_attr(test, assert_instr(vtrunohb))]
11664#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11665pub unsafe fn Q6_P_vtrunohb_PP(rss: i64, rtt: i64) -> i64 {
11666    hexagon_S6_vtrunohb_ppp(rss, rtt)
11667}
11668
11669/// `Pd4=!any8(vcmpb.eq(Rss32,Rtt32))`
11670///
11671/// Instruction Type: ALU64
11672/// Execution Slots: SLOT23
11673/// Requires: V65
11674#[inline]
11675#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v65"))]
11676#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11677pub unsafe fn Q6_p_not_any8_vcmpb_eq_PP(rss: i64, rtt: i64) -> i32 {
11678    hexagon_A6_vcmpbeq_notany(rss, rtt)
11679}
11680
11681/// `Rdd32=dfadd(Rss32,Rtt32)`
11682///
11683/// Instruction Type: M
11684/// Execution Slots: SLOT23
11685/// Requires: V66
11686#[inline]
11687#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))]
11688#[cfg_attr(test, assert_instr(dfadd))]
11689#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11690pub unsafe fn Q6_P_dfadd_PP(rss: f64, rtt: f64) -> f64 {
11691    hexagon_F2_dfadd(rss, rtt)
11692}
11693
11694/// `Rdd32=dfsub(Rss32,Rtt32)`
11695///
11696/// Instruction Type: M
11697/// Execution Slots: SLOT23
11698/// Requires: V66
11699#[inline]
11700#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))]
11701#[cfg_attr(test, assert_instr(dfsub))]
11702#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11703pub unsafe fn Q6_P_dfsub_PP(rss: f64, rtt: f64) -> f64 {
11704    hexagon_F2_dfsub(rss, rtt)
11705}
11706
11707/// `Rx32-=mpyi(Rs32,Rt32)`
11708///
11709/// Instruction Type: M
11710/// Execution Slots: SLOT23
11711/// Requires: V66
11712#[inline]
11713#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))]
11714#[cfg_attr(test, assert_instr(mpyi))]
11715#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11716pub unsafe fn Q6_R_mpyinac_RR(rx: i32, rs: i32, rt: i32) -> i32 {
11717    hexagon_M2_mnaci(rx, rs, rt)
11718}
11719
11720/// `Rd32=mask(#u5,#U5)`
11721///
11722/// Instruction Type: S_2op
11723/// Execution Slots: SLOT23
11724/// Requires: V66
11725#[inline]
11726#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))]
11727#[rustc_legacy_const_generics(0, 1)]
11728#[cfg_attr(test, assert_instr(mask, IU5 = 0, IU5_2 = 0))]
11729#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11730pub unsafe fn Q6_R_mask_II<const IU5: u32, const IU5_2: u32>() -> i32 {
11731    static_assert_uimm_bits!(IU5, 5);
11732    static_assert_uimm_bits!(IU5_2, 5);
11733    hexagon_S2_mask(IU5 as i32, IU5_2 as i32)
11734}
11735
11736/// `Rd32=clip(Rs32,#u5)`
11737///
11738/// Instruction Type: S_2op
11739/// Execution Slots: SLOT23
11740/// Requires: V67, Audio
11741#[inline]
11742#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11743#[rustc_legacy_const_generics(1)]
11744#[cfg_attr(test, assert_instr(clip, IU5 = 0))]
11745#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11746pub unsafe fn Q6_R_clip_RI<const IU5: u32>(rs: i32) -> i32 {
11747    static_assert_uimm_bits!(IU5, 5);
11748    hexagon_A7_clip(rs, IU5 as i32)
11749}
11750
11751/// `Rdd32=cround(Rss32,#u6)`
11752///
11753/// Instruction Type: S_2op
11754/// Execution Slots: SLOT23
11755/// Requires: V67, Audio
11756#[inline]
11757#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11758#[rustc_legacy_const_generics(1)]
11759#[cfg_attr(test, assert_instr(cround, IU6 = 0))]
11760#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11761pub unsafe fn Q6_P_cround_PI<const IU6: u32>(rss: i64) -> i64 {
11762    static_assert_uimm_bits!(IU6, 6);
11763    hexagon_A7_croundd_ri(rss, IU6 as i32)
11764}
11765
11766/// `Rdd32=cround(Rss32,Rt32)`
11767///
11768/// Instruction Type: S_3op
11769/// Execution Slots: SLOT23
11770/// Requires: V67, Audio
11771#[inline]
11772#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11773#[cfg_attr(test, assert_instr(cround))]
11774#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11775pub unsafe fn Q6_P_cround_PR(rss: i64, rt: i32) -> i64 {
11776    hexagon_A7_croundd_rr(rss, rt)
11777}
11778
11779/// `Rdd32=vclip(Rss32,#u5)`
11780///
11781/// Instruction Type: S_2op
11782/// Execution Slots: SLOT23
11783/// Requires: V67, Audio
11784#[inline]
11785#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11786#[rustc_legacy_const_generics(1)]
11787#[cfg_attr(test, assert_instr(vclip, IU5 = 0))]
11788#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11789pub unsafe fn Q6_P_vclip_PI<const IU5: u32>(rss: i64) -> i64 {
11790    static_assert_uimm_bits!(IU5, 5);
11791    hexagon_A7_vclip(rss, IU5 as i32)
11792}
11793
11794/// `Rdd32=dfmax(Rss32,Rtt32)`
11795///
11796/// Instruction Type: M
11797/// Execution Slots: SLOT23
11798/// Requires: V67
11799#[inline]
11800#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))]
11801#[cfg_attr(test, assert_instr(dfmax))]
11802#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11803pub unsafe fn Q6_P_dfmax_PP(rss: f64, rtt: f64) -> f64 {
11804    hexagon_F2_dfmax(rss, rtt)
11805}
11806
11807/// `Rdd32=dfmin(Rss32,Rtt32)`
11808///
11809/// Instruction Type: M
11810/// Execution Slots: SLOT23
11811/// Requires: V67
11812#[inline]
11813#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))]
11814#[cfg_attr(test, assert_instr(dfmin))]
11815#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11816pub unsafe fn Q6_P_dfmin_PP(rss: f64, rtt: f64) -> f64 {
11817    hexagon_F2_dfmin(rss, rtt)
11818}
11819
11820/// `Rdd32=dfmpyfix(Rss32,Rtt32)`
11821///
11822/// Instruction Type: M
11823/// Execution Slots: SLOT23
11824/// Requires: V67
11825#[inline]
11826#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))]
11827#[cfg_attr(test, assert_instr(dfmpyfix))]
11828#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11829pub unsafe fn Q6_P_dfmpyfix_PP(rss: f64, rtt: f64) -> f64 {
11830    hexagon_F2_dfmpyfix(rss, rtt)
11831}
11832
11833/// `Rxx32+=dfmpyhh(Rss32,Rtt32)`
11834///
11835/// Instruction Type: M
11836/// Execution Slots: SLOT23
11837/// Requires: V67
11838#[inline]
11839#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))]
11840#[cfg_attr(test, assert_instr(dfmpyhh))]
11841#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11842pub unsafe fn Q6_P_dfmpyhhacc_PP(rxx: f64, rss: f64, rtt: f64) -> f64 {
11843    hexagon_F2_dfmpyhh(rxx, rss, rtt)
11844}
11845
11846/// `Rxx32+=dfmpylh(Rss32,Rtt32)`
11847///
11848/// Instruction Type: M
11849/// Execution Slots: SLOT23
11850/// Requires: V67
11851#[inline]
11852#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))]
11853#[cfg_attr(test, assert_instr(dfmpylh))]
11854#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11855pub unsafe fn Q6_P_dfmpylhacc_PP(rxx: f64, rss: f64, rtt: f64) -> f64 {
11856    hexagon_F2_dfmpylh(rxx, rss, rtt)
11857}
11858
11859/// `Rdd32=dfmpyll(Rss32,Rtt32)`
11860///
11861/// Instruction Type: M
11862/// Execution Slots: SLOT23
11863/// Requires: V67
11864#[inline]
11865#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67"))]
11866#[cfg_attr(test, assert_instr(dfmpyll))]
11867#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11868pub unsafe fn Q6_P_dfmpyll_PP(rss: f64, rtt: f64) -> f64 {
11869    hexagon_F2_dfmpyll(rss, rtt)
11870}
11871
11872/// `Rdd32=cmpyiw(Rss32,Rtt32)`
11873///
11874/// Instruction Type: M
11875/// Execution Slots: SLOT3
11876/// Requires: V67, Audio
11877#[inline]
11878#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11879#[cfg_attr(test, assert_instr(cmpyiw))]
11880#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11881pub unsafe fn Q6_P_cmpyiw_PP(rss: i64, rtt: i64) -> i64 {
11882    hexagon_M7_dcmpyiw(rss, rtt)
11883}
11884
11885/// `Rxx32+=cmpyiw(Rss32,Rtt32)`
11886///
11887/// Instruction Type: M
11888/// Execution Slots: SLOT3
11889/// Requires: V67, Audio
11890#[inline]
11891#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11892#[cfg_attr(test, assert_instr(cmpyiw))]
11893#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11894pub unsafe fn Q6_P_cmpyiwacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
11895    hexagon_M7_dcmpyiw_acc(rxx, rss, rtt)
11896}
11897
11898/// `Rdd32=cmpyiw(Rss32,Rtt32*)`
11899///
11900/// Instruction Type: M
11901/// Execution Slots: SLOT3
11902/// Requires: V67, Audio
11903#[inline]
11904#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11905#[cfg_attr(test, assert_instr(cmpyiw))]
11906#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11907pub unsafe fn Q6_P_cmpyiw_PP_conj(rss: i64, rtt: i64) -> i64 {
11908    hexagon_M7_dcmpyiwc(rss, rtt)
11909}
11910
11911/// `Rxx32+=cmpyiw(Rss32,Rtt32*)`
11912///
11913/// Instruction Type: M
11914/// Execution Slots: SLOT3
11915/// Requires: V67, Audio
11916#[inline]
11917#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11918#[cfg_attr(test, assert_instr(cmpyiw))]
11919#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11920pub unsafe fn Q6_P_cmpyiwacc_PP_conj(rxx: i64, rss: i64, rtt: i64) -> i64 {
11921    hexagon_M7_dcmpyiwc_acc(rxx, rss, rtt)
11922}
11923
11924/// `Rdd32=cmpyrw(Rss32,Rtt32)`
11925///
11926/// Instruction Type: M
11927/// Execution Slots: SLOT3
11928/// Requires: V67, Audio
11929#[inline]
11930#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11931#[cfg_attr(test, assert_instr(cmpyrw))]
11932#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11933pub unsafe fn Q6_P_cmpyrw_PP(rss: i64, rtt: i64) -> i64 {
11934    hexagon_M7_dcmpyrw(rss, rtt)
11935}
11936
11937/// `Rxx32+=cmpyrw(Rss32,Rtt32)`
11938///
11939/// Instruction Type: M
11940/// Execution Slots: SLOT3
11941/// Requires: V67, Audio
11942#[inline]
11943#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11944#[cfg_attr(test, assert_instr(cmpyrw))]
11945#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11946pub unsafe fn Q6_P_cmpyrwacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
11947    hexagon_M7_dcmpyrw_acc(rxx, rss, rtt)
11948}
11949
11950/// `Rdd32=cmpyrw(Rss32,Rtt32*)`
11951///
11952/// Instruction Type: M
11953/// Execution Slots: SLOT3
11954/// Requires: V67, Audio
11955#[inline]
11956#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11957#[cfg_attr(test, assert_instr(cmpyrw))]
11958#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11959pub unsafe fn Q6_P_cmpyrw_PP_conj(rss: i64, rtt: i64) -> i64 {
11960    hexagon_M7_dcmpyrwc(rss, rtt)
11961}
11962
11963/// `Rxx32+=cmpyrw(Rss32,Rtt32*)`
11964///
11965/// Instruction Type: M
11966/// Execution Slots: SLOT3
11967/// Requires: V67, Audio
11968#[inline]
11969#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11970#[cfg_attr(test, assert_instr(cmpyrw))]
11971#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11972pub unsafe fn Q6_P_cmpyrwacc_PP_conj(rxx: i64, rss: i64, rtt: i64) -> i64 {
11973    hexagon_M7_dcmpyrwc_acc(rxx, rss, rtt)
11974}
11975
11976/// `Rdd32=vdmpyw(Rss32,Rtt32)`
11977///
11978/// Instruction Type: M
11979/// Execution Slots: SLOT3
11980/// Requires: V67, Audio
11981#[inline]
11982#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11983#[cfg_attr(test, assert_instr(vdmpyw))]
11984#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11985pub unsafe fn Q6_P_vdmpyw_PP(rss: i64, rtt: i64) -> i64 {
11986    hexagon_M7_vdmpy(rss, rtt)
11987}
11988
11989/// `Rxx32+=vdmpyw(Rss32,Rtt32)`
11990///
11991/// Instruction Type: M
11992/// Execution Slots: SLOT3
11993/// Requires: V67, Audio
11994#[inline]
11995#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
11996#[cfg_attr(test, assert_instr(vdmpyw))]
11997#[unstable(feature = "stdarch_hexagon", issue = "151523")]
11998pub unsafe fn Q6_P_vdmpywacc_PP(rxx: i64, rss: i64, rtt: i64) -> i64 {
11999    hexagon_M7_vdmpy_acc(rxx, rss, rtt)
12000}
12001
12002/// `Rd32=cmpyiw(Rss32,Rtt32):<<1:sat`
12003///
12004/// Instruction Type: M
12005/// Execution Slots: SLOT3
12006/// Requires: V67, Audio
12007#[inline]
12008#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
12009#[cfg_attr(test, assert_instr(cmpyiw))]
12010#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12011pub unsafe fn Q6_R_cmpyiw_PP_s1_sat(rss: i64, rtt: i64) -> i32 {
12012    hexagon_M7_wcmpyiw(rss, rtt)
12013}
12014
12015/// `Rd32=cmpyiw(Rss32,Rtt32):<<1:rnd:sat`
12016///
12017/// Instruction Type: M
12018/// Execution Slots: SLOT3
12019/// Requires: V67, Audio
12020#[inline]
12021#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
12022#[cfg_attr(test, assert_instr(cmpyiw))]
12023#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12024pub unsafe fn Q6_R_cmpyiw_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i32 {
12025    hexagon_M7_wcmpyiw_rnd(rss, rtt)
12026}
12027
12028/// `Rd32=cmpyiw(Rss32,Rtt32*):<<1:sat`
12029///
12030/// Instruction Type: M
12031/// Execution Slots: SLOT3
12032/// Requires: V67, Audio
12033#[inline]
12034#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
12035#[cfg_attr(test, assert_instr(cmpyiw))]
12036#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12037pub unsafe fn Q6_R_cmpyiw_PP_conj_s1_sat(rss: i64, rtt: i64) -> i32 {
12038    hexagon_M7_wcmpyiwc(rss, rtt)
12039}
12040
12041/// `Rd32=cmpyiw(Rss32,Rtt32*):<<1:rnd:sat`
12042///
12043/// Instruction Type: M
12044/// Execution Slots: SLOT3
12045/// Requires: V67, Audio
12046#[inline]
12047#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
12048#[cfg_attr(test, assert_instr(cmpyiw))]
12049#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12050pub unsafe fn Q6_R_cmpyiw_PP_conj_s1_rnd_sat(rss: i64, rtt: i64) -> i32 {
12051    hexagon_M7_wcmpyiwc_rnd(rss, rtt)
12052}
12053
12054/// `Rd32=cmpyrw(Rss32,Rtt32):<<1:sat`
12055///
12056/// Instruction Type: M
12057/// Execution Slots: SLOT3
12058/// Requires: V67, Audio
12059#[inline]
12060#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
12061#[cfg_attr(test, assert_instr(cmpyrw))]
12062#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12063pub unsafe fn Q6_R_cmpyrw_PP_s1_sat(rss: i64, rtt: i64) -> i32 {
12064    hexagon_M7_wcmpyrw(rss, rtt)
12065}
12066
12067/// `Rd32=cmpyrw(Rss32,Rtt32):<<1:rnd:sat`
12068///
12069/// Instruction Type: M
12070/// Execution Slots: SLOT3
12071/// Requires: V67, Audio
12072#[inline]
12073#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
12074#[cfg_attr(test, assert_instr(cmpyrw))]
12075#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12076pub unsafe fn Q6_R_cmpyrw_PP_s1_rnd_sat(rss: i64, rtt: i64) -> i32 {
12077    hexagon_M7_wcmpyrw_rnd(rss, rtt)
12078}
12079
12080/// `Rd32=cmpyrw(Rss32,Rtt32*):<<1:sat`
12081///
12082/// Instruction Type: M
12083/// Execution Slots: SLOT3
12084/// Requires: V67, Audio
12085#[inline]
12086#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
12087#[cfg_attr(test, assert_instr(cmpyrw))]
12088#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12089pub unsafe fn Q6_R_cmpyrw_PP_conj_s1_sat(rss: i64, rtt: i64) -> i32 {
12090    hexagon_M7_wcmpyrwc(rss, rtt)
12091}
12092
12093/// `Rd32=cmpyrw(Rss32,Rtt32*):<<1:rnd:sat`
12094///
12095/// Instruction Type: M
12096/// Execution Slots: SLOT3
12097/// Requires: V67, Audio
12098#[inline]
12099#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))]
12100#[cfg_attr(test, assert_instr(cmpyrw))]
12101#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12102pub unsafe fn Q6_R_cmpyrw_PP_conj_s1_rnd_sat(rss: i64, rtt: i64) -> i32 {
12103    hexagon_M7_wcmpyrwc_rnd(rss, rtt)
12104}
12105
12106/// `dmlink(Rs32,Rt32)`
12107///
12108/// Instruction Type: ST
12109/// Execution Slots: SLOT0
12110/// Requires: V68
12111#[inline]
12112#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))]
12113#[cfg_attr(test, assert_instr(dmlink))]
12114#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12115pub unsafe fn Q6_dmlink_AA(rs: i32, rt: i32) {
12116    hexagon_Y6_dmlink(rs, rt)
12117}
12118
12119/// `Rd32=dmpause`
12120///
12121/// Instruction Type: ST
12122/// Execution Slots: SLOT0
12123/// Requires: V68
12124#[inline]
12125#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))]
12126#[cfg_attr(test, assert_instr(dmpause))]
12127#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12128pub unsafe fn Q6_R_dmpause() -> i32 {
12129    hexagon_Y6_dmpause()
12130}
12131
12132/// `Rd32=dmpoll`
12133///
12134/// Instruction Type: ST
12135/// Execution Slots: SLOT0
12136/// Requires: V68
12137#[inline]
12138#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))]
12139#[cfg_attr(test, assert_instr(dmpoll))]
12140#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12141pub unsafe fn Q6_R_dmpoll() -> i32 {
12142    hexagon_Y6_dmpoll()
12143}
12144
12145/// `dmresume(Rs32)`
12146///
12147/// Instruction Type: ST
12148/// Execution Slots: SLOT0
12149/// Requires: V68
12150#[inline]
12151#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))]
12152#[cfg_attr(test, assert_instr(dmresume))]
12153#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12154pub unsafe fn Q6_dmresume_A(rs: i32) {
12155    hexagon_Y6_dmresume(rs)
12156}
12157
12158/// `dmstart(Rs32)`
12159///
12160/// Instruction Type: ST
12161/// Execution Slots: SLOT0
12162/// Requires: V68
12163#[inline]
12164#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))]
12165#[cfg_attr(test, assert_instr(dmstart))]
12166#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12167pub unsafe fn Q6_dmstart_A(rs: i32) {
12168    hexagon_Y6_dmstart(rs)
12169}
12170
12171/// `Rd32=dmwait`
12172///
12173/// Instruction Type: ST
12174/// Execution Slots: SLOT0
12175/// Requires: V68
12176#[inline]
12177#[cfg_attr(target_arch = "hexagon", target_feature(enable = "v68"))]
12178#[cfg_attr(test, assert_instr(dmwait))]
12179#[unstable(feature = "stdarch_hexagon", issue = "151523")]
12180pub unsafe fn Q6_R_dmwait() -> i32 {
12181    hexagon_Y6_dmwait()
12182}
core/stdarch/crates/core_arch/src/hexagon/scalar.rs

core/stdarch/crates/core_arch/src/hexagon/
scalar.rs
