[^:]*: Assembler messages:
[^:]*:4: Error: bad type in SIMD instruction -- `vshr.s64 q0,q1,#1'
[^:]*:5: Error: bad type in SIMD instruction -- `vshr.i32 q0,q1,#1'
[^:]*:6: Error: bad type in SIMD instruction -- `vrshr.u64 q0,q1,#1'
[^:]*:7: Error: bad type in SIMD instruction -- `vrshr.i32 q0,q1,#1'
[^:]*:8: Error: immediate out of range for shift -- `vshr.s8 q0,q1,#9'
[^:]*:9: Error: immediate out of range for shift -- `vshr.u8 q0,q1,#9'
[^:]*:10: Error: immediate out of range for shift -- `vshr.s16 q0,q1,#17'
[^:]*:11: Error: immediate out of range for shift -- `vshr.u16 q0,q1,#17'
[^:]*:12: Error: immediate out of range for shift -- `vshr.s32 q0,q1,#33'
[^:]*:13: Error: immediate out of range for shift -- `vshr.u32 q0,q1,#33'
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:23: Error: syntax error -- `vshreq.s32 q0,q1,#1'
[^:]*:24: Error: syntax error -- `vshreq.s32 q0,q1,#1'
[^:]*:26: Error: syntax error -- `vshreq.s32 q0,q1,#1'
[^:]*:27: Error: vector predicated instruction should be in VPT/VPST block -- `vshrt.s32 q0,q1,#1'
[^:]*:29: Error: instruction missing MVE vector predication code -- `vshr.s32 q0,q1,#1'
[^:]*:31: Error: syntax error -- `vrshreq.s32 q0,q1,#1'
[^:]*:32: Error: syntax error -- `vrshreq.s32 q0,q1,#1'
[^:]*:34: Error: syntax error -- `vrshreq.s32 q0,q1,#1'
[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vrshrt.s32 q0,q1,#1'
[^:]*:37: Error: instruction missing MVE vector predication code -- `vrshr.s32 q0,q1,#1'
