#ifndef __ASM_OFFSETS_H__
#define __ASM_OFFSETS_H__
/*
 * DO NOT MODIFY.
 *
 * This file was generated by Kbuild
 */

#define TSK_ACTIVE_MM 1684 /* offsetof(struct task_struct, active_mm) */
#define TSK_STACK_CANARY 1776 /* offsetof(struct task_struct, stack_canary) */

#define TI_FLAGS 0 /* offsetof(struct thread_info, flags) */
#define TI_PREEMPT 4 /* offsetof(struct thread_info, preempt_count) */
#define TI_CPU 8 /* offsetof(struct thread_info, cpu) */
#define TI_CPU_DOMAIN 12 /* offsetof(struct thread_info, cpu_domain) */
#define TI_CPU_SAVE 16 /* offsetof(struct thread_info, cpu_context) */
#define TI_ABI_SYSCALL 64 /* offsetof(struct thread_info, abi_syscall) */
#define TI_TP_VALUE 68 /* offsetof(struct thread_info, tp_value) */
#define TI_FPSTATE 80 /* offsetof(struct thread_info, fpstate) */
#define TI_VFPSTATE 224 /* offsetof(struct thread_info, vfpstate) */
#define VFP_CPU 272 /* offsetof(union vfp_state, hard.cpu) */
#define SOFTIRQ_DISABLE_OFFSET 512 /* SOFTIRQ_DISABLE_OFFSET */
#define TI_THUMBEE_STATE 504 /* offsetof(struct thread_info, thumbee_state) */

#define S_R0 0 /* offsetof(struct pt_regs, ARM_r0) */
#define S_R1 4 /* offsetof(struct pt_regs, ARM_r1) */
#define S_R2 8 /* offsetof(struct pt_regs, ARM_r2) */
#define S_R3 12 /* offsetof(struct pt_regs, ARM_r3) */
#define S_R4 16 /* offsetof(struct pt_regs, ARM_r4) */
#define S_R5 20 /* offsetof(struct pt_regs, ARM_r5) */
#define S_R6 24 /* offsetof(struct pt_regs, ARM_r6) */
#define S_R7 28 /* offsetof(struct pt_regs, ARM_r7) */
#define S_R8 32 /* offsetof(struct pt_regs, ARM_r8) */
#define S_R9 36 /* offsetof(struct pt_regs, ARM_r9) */
#define S_R10 40 /* offsetof(struct pt_regs, ARM_r10) */
#define S_FP 44 /* offsetof(struct pt_regs, ARM_fp) */
#define S_IP 48 /* offsetof(struct pt_regs, ARM_ip) */
#define S_SP 52 /* offsetof(struct pt_regs, ARM_sp) */
#define S_LR 56 /* offsetof(struct pt_regs, ARM_lr) */
#define S_PC 60 /* offsetof(struct pt_regs, ARM_pc) */
#define S_PSR 64 /* offsetof(struct pt_regs, ARM_cpsr) */
#define S_OLD_R0 68 /* offsetof(struct pt_regs, ARM_ORIG_r0) */
#define PT_REGS_SIZE 72 /* sizeof(struct pt_regs) */
#define SVC_DACR 72 /* offsetof(struct svc_pt_regs, dacr) */
#define SVC_TTBCR 76 /* offsetof(struct svc_pt_regs, ttbcr) */
#define SVC_REGS_SIZE 80 /* sizeof(struct svc_pt_regs) */

#define SIGFRAME_RC3_OFFSET 756 /* offsetof(struct sigframe, retcode[3]) */
#define RT_SIGFRAME_RC3_OFFSET 884 /* offsetof(struct rt_sigframe, sig.retcode[3]) */

#define L2X0_R_PHY_BASE 0 /* offsetof(struct l2x0_regs, phy_base) */
#define L2X0_R_AUX_CTRL 4 /* offsetof(struct l2x0_regs, aux_ctrl) */
#define L2X0_R_TAG_LATENCY 8 /* offsetof(struct l2x0_regs, tag_latency) */
#define L2X0_R_DATA_LATENCY 12 /* offsetof(struct l2x0_regs, data_latency) */
#define L2X0_R_FILTER_START 16 /* offsetof(struct l2x0_regs, filter_start) */
#define L2X0_R_FILTER_END 20 /* offsetof(struct l2x0_regs, filter_end) */
#define L2X0_R_PREFETCH_CTRL 24 /* offsetof(struct l2x0_regs, prefetch_ctrl) */
#define L2X0_R_PWR_CTRL 28 /* offsetof(struct l2x0_regs, pwr_ctrl) */

#define MM_CONTEXT_ID 776 /* offsetof(struct mm_struct, context.id.counter) */

#define VMA_VM_MM 8 /* offsetof(struct vm_area_struct, vm_mm) */
#define VMA_VM_FLAGS 16 /* offsetof(struct vm_area_struct, vm_flags) */

#define VM_EXEC 4 /* VM_EXEC */

#define PAGE_SZ 4096 /* PAGE_SIZE */

#define SYS_ERROR0 10420224 /* 0x9f0000 */

#define SIZEOF_MACHINE_DESC 104 /* sizeof(struct machine_desc) */
#define MACHINFO_TYPE 0 /* offsetof(struct machine_desc, nr) */
#define MACHINFO_NAME 4 /* offsetof(struct machine_desc, name) */

#define PROC_INFO_SZ 52 /* sizeof(struct proc_info_list) */
#define PROCINFO_INITFUNC 16 /* offsetof(struct proc_info_list, __cpu_flush) */
#define PROCINFO_MM_MMUFLAGS 8 /* offsetof(struct proc_info_list, __cpu_mm_mmu_flags) */
#define PROCINFO_IO_MMUFLAGS 12 /* offsetof(struct proc_info_list, __cpu_io_mmu_flags) */

#define CPU_SLEEP_SIZE 40 /* offsetof(struct processor, suspend_size) */
#define CPU_DO_SUSPEND 44 /* offsetof(struct processor, do_suspend) */
#define CPU_DO_RESUME 48 /* offsetof(struct processor, do_resume) */
#define SLEEP_SAVE_SP_SZ 8 /* sizeof(struct sleep_save_sp) */
#define SLEEP_SAVE_SP_PHYS 4 /* offsetof(struct sleep_save_sp, save_ptr_stash_phys) */
#define SLEEP_SAVE_SP_VIRT 0 /* offsetof(struct sleep_save_sp, save_ptr_stash) */
#define ARM_SMCCC_QUIRK_ID_OFFS 0 /* offsetof(struct arm_smccc_quirk, id) */
#define ARM_SMCCC_QUIRK_STATE_OFFS 4 /* offsetof(struct arm_smccc_quirk, state) */

#define DMA_BIDIRECTIONAL 0 /* DMA_BIDIRECTIONAL */
#define DMA_TO_DEVICE 1 /* DMA_TO_DEVICE */
#define DMA_FROM_DEVICE 2 /* DMA_FROM_DEVICE */

#define CACHE_WRITEBACK_ORDER 6 /* __CACHE_WRITEBACK_ORDER */
#define CACHE_WRITEBACK_GRANULE 64 /* __CACHE_WRITEBACK_GRANULE */

#define KEXEC_START_ADDR 0 /* offsetof(struct kexec_relocate_data, kexec_start_address) */
#define KEXEC_INDIR_PAGE 4 /* offsetof(struct kexec_relocate_data, kexec_indirection_page) */
#define KEXEC_MACH_TYPE 8 /* offsetof(struct kexec_relocate_data, kexec_mach_type) */
#define KEXEC_R2 12 /* offsetof(struct kexec_relocate_data, kexec_r2) */

#endif
